Project Information c:\max2work\kumagai\univ_if\uifbase\uif10k_ramrw.rpt MAX+plus II Compiler Report File Version 10.1 06/12/2001 Compiled: 02/07/2003 15:42:21 Copyright (C) 1988-2001 Altera Corporation Any megafunction design, and related net list (encrypted or decrypted), support information, device programming or simulation file, and any other associated documentation or information provided by Altera or a partner under Altera's Megafunction Partnership Program may be used only to program PLD devices (but not masked PLD devices) from Altera. Any other use of such megafunction design, net list, support information, device programming or simulation file, or any other related documentation or information is prohibited for any other purpose, including, but not limited to modification, reverse engineering, de-compiling, or use with any other silicon devices, unless such use is explicitly licensed under a separate agreement with Altera or a megafunction partner. Title to the intellectual property, including patents, copyrights, trademarks, trade secrets, or maskworks, embodied in any such megafunction design, net list, support information, device programming or simulation file, or any other related documentation or information provided by Altera or a megafunction partner, remains with Altera, the megafunction partner, or their respective licensors. No other licenses, including any licenses needed under any third party's intellectual property, are provided herein. ***** Project compilation was successful ** DEVICE SUMMARY ** Chip/ Input Output Bidir Memory Memory LCs POF Device Pins Pins Pins Bits % Utilized LCs % Utilized uif10k_ramrw EPF10K30AQC208-2 42 20 65 0 0 % 96 5 % User Pins: 42 20 65 Project Information c:\max2work\kumagai\univ_if\uifbase\uif10k_ramrw.rpt ** PROJECT COMPILATION MESSAGES ** Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:21|dout7' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:21|dout6' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:21|dout5' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:21|dout4' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:21|dout3' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:21|dout2' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:21|dout1' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:21|dout0' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:12|dout7' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:12|dout6' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:12|dout5' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:12|dout4' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:12|dout3' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:12|dout2' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:12|dout1' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:12|dout0' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:1|dout7' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:1|dout6' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:1|dout5' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:1|dout4' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:1|dout3' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:1|dout2' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:1|dout1' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:1|dout0' is permanently disabled Warning: TRI or OPNDRN buffer ':98' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:21|dout7' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:21|dout6' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:21|dout5' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:21|dout4' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:21|dout3' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:21|dout2' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:21|dout1' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:21|dout0' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:12|dout7' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:12|dout6' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:12|dout5' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:12|dout4' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:12|dout3' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:12|dout2' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:12|dout1' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:12|dout0' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:1|dout7' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:1|dout6' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:1|dout5' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:1|dout4' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:1|dout3' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:1|dout2' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:1|dout1' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:1|dout0' is permanently disabled Warning: TRI or OPNDRN buffer ':98' is permanently disabled Info: Reserved unused input pin 'TA16' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board Info: Reserved unused input pin 'TA15' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board Info: Reserved unused input pin 'TA14' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board Info: Reserved unused input pin 'TA13' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board Info: Reserved unused input pin 'TA12' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board Info: Reserved unused input pin 'TA11' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board Info: Reserved unused input pin 'TA10' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board Info: Reserved unused input pin 'TA9' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board Info: Reserved unused input pin 'TA8' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board Info: Reserved unused input pin 'TA7' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board Info: Reserved unused input pin 'TA6' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board Info: Reserved unused input pin 'TA5' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board Info: Reserved unused input pin 'TA4' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board Info: Reserved unused input pin 'TA3' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board Info: Reserved unused input pin 'TA2' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board Info: Reserved unused input pin 'TA0' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board Info: Reserved unused input pin 'ExtClock1' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board Info: Reserved unused input pin '/TOUT' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board Info: Reserved unused input pin '/TRESET' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board Info: Reserved unused input pin '/IRC3' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board Info: Reserved unused input pin '/IRC2' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board Info: Reserved unused input pin '/IRC1' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board Info: Reserved unused input pin '/IRC0' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board Info: Reserved unused input pin '/IORACK' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board Info: Reserved unused input pin '/MEMCS' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board Info: Reserved unused input pin '/ROMCS' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board Info: Reserved unused input pin '/MRD' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board Info: Reserved unused input pin '/MWR' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board Info: Reserved unused input pin '/IOR' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board Info: Reserved unused input pin '/IOCS7' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board Info: Reserved unused input pin '/IOCS6' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board Info: Reserved unused input pin '/IOCS5' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board Info: Reserved unused input pin '/IOCS4' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board Info: Reserved unused input pin '/IOCS3' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board Info: Reserved unused input pin '/IOCS1' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board Info: Reserved unused input pin '/IOCS0' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board Info: Reserved unused input pin '/BHE' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board Project Information c:\max2work\kumagai\univ_if\uifbase\uif10k_ramrw.rpt ** PIN/LOCATION/CHIP ASSIGNMENTS ** Actual User Assignments Assignments (if different) Node Name uif10k_ramrw@79 BCLK uif10k_ramrw@47 /BHE uif10k_ramrw@183 ExtClock0 uif10k_ramrw@182 ExtClock1 uif10k_ramrw@208 ExtIO0 uif10k_ramrw@207 ExtIO1 uif10k_ramrw@7 IOA_DIR uif10k_ramrw@8 IOA_EN uif10k_ramrw@205 IOA0 uif10k_ramrw@203 IOA1 uif10k_ramrw@202 IOA2 uif10k_ramrw@200 IOA3 uif10k_ramrw@199 IOA4 uif10k_ramrw@198 IOA5 uif10k_ramrw@197 IOA6 uif10k_ramrw@196 IOA7 uif10k_ramrw@193 IOB_DIR uif10k_ramrw@195 IOB_EN uif10k_ramrw@192 IOB0 uif10k_ramrw@191 IOB1 uif10k_ramrw@190 IOB2 uif10k_ramrw@189 IOB3 uif10k_ramrw@187 IOB4 uif10k_ramrw@179 IOB5 uif10k_ramrw@177 IOB6 uif10k_ramrw@176 IOB7 uif10k_ramrw@174 IOC_DIR uif10k_ramrw@175 IOC_EN uif10k_ramrw@9 /IOCS0 uif10k_ramrw@11 /IOCS1 uif10k_ramrw@12 /IOCS2 uif10k_ramrw@13 /IOCS3 uif10k_ramrw@14 /IOCS4 uif10k_ramrw@15 /IOCS5 uif10k_ramrw@17 /IOCS6 uif10k_ramrw@18 /IOCS7 uif10k_ramrw@173 IOC0 uif10k_ramrw@172 IOC1 uif10k_ramrw@170 IOC2 uif10k_ramrw@169 IOC3 uif10k_ramrw@168 IOC4 uif10k_ramrw@167 IOC5 uif10k_ramrw@163 IOC6 uif10k_ramrw@160 IOC7 uif10k_ramrw@149 IOD_DIR uif10k_ramrw@150 IOD_EN uif10k_ramrw@148 IOD0 uif10k_ramrw@147 IOD1 uif10k_ramrw@144 IOD2 uif10k_ramrw@143 IOD3 uif10k_ramrw@142 IOD4 uif10k_ramrw@141 IOD5 uif10k_ramrw@140 IOD6 uif10k_ramrw@139 IOD7 uif10k_ramrw@135 IOE_DIR uif10k_ramrw@136 IOE_EN uif10k_ramrw@134 IOE0 uif10k_ramrw@133 IOE1 uif10k_ramrw@132 IOE2 uif10k_ramrw@131 IOE3 uif10k_ramrw@128 IOE4 uif10k_ramrw@127 IOE5 uif10k_ramrw@126 IOE6 uif10k_ramrw@125 IOE7 uif10k_ramrw@121 IOF_DIR uif10k_ramrw@122 IOF_EN uif10k_ramrw@120 IOF0 uif10k_ramrw@119 IOF1 uif10k_ramrw@116 IOF2 uif10k_ramrw@115 IOF3 uif10k_ramrw@114 IOF4 uif10k_ramrw@113 IOF5 uif10k_ramrw@112 IOF6 uif10k_ramrw@111 IOF7 uif10k_ramrw@83 /IOR uif10k_ramrw@88 /IORACK uif10k_ramrw@86 IORDY uif10k_ramrw@87 /IORREQ uif10k_ramrw@85 /IOW uif10k_ramrw@94 /IRC0 uif10k_ramrw@95 /IRC1 uif10k_ramrw@96 /IRC2 uif10k_ramrw@97 /IRC3 uif10k_ramrw@89 IRQ0 uif10k_ramrw@90 IRQ1 uif10k_ramrw@92 IRQ2 uif10k_ramrw@93 IRQ3 uif10k_ramrw@71 /MEMCS uif10k_ramrw@74 /MRD uif10k_ramrw@75 /MWR uif10k_ramrw@73 /ROMCS uif10k_ramrw@46 TA0 uif10k_ramrw@45 TA1 uif10k_ramrw@44 TA2 uif10k_ramrw@41 TA3 uif10k_ramrw@40 TA4 uif10k_ramrw@39 TA5 uif10k_ramrw@38 TA6 uif10k_ramrw@37 TA7 uif10k_ramrw@36 TA8 uif10k_ramrw@31 TA9 uif10k_ramrw@30 TA10 uif10k_ramrw@29 TA11 uif10k_ramrw@28 TA12 uif10k_ramrw@27 TA13 uif10k_ramrw@26 TA14 uif10k_ramrw@25 TA15 uif10k_ramrw@24 TA16 uif10k_ramrw@99 TCLK uif10k_ramrw@53 TD0 uif10k_ramrw@54 TD1 uif10k_ramrw@55 TD2 uif10k_ramrw@56 TD3 uif10k_ramrw@57 TD4 uif10k_ramrw@58 TD5 uif10k_ramrw@60 TD6 uif10k_ramrw@61 TD7 uif10k_ramrw@62 TD8 uif10k_ramrw@63 TD9 uif10k_ramrw@64 TD10 uif10k_ramrw@65 TD11 uif10k_ramrw@67 TD12 uif10k_ramrw@68 TD13 uif10k_ramrw@69 TD14 uif10k_ramrw@70 TD15 uif10k_ramrw@100 /TOUT uif10k_ramrw@78 /TRESET Project Information c:\max2work\kumagai\univ_if\uifbase\uif10k_ramrw.rpt ** FILE HIERARCHY ** |lpm_bustri:21| |lpm_bustri:12| |lpm_bustri:1| |lpm_bustri:45| |uif_ramif:219| |uif_ramif:219|lpm_bustri:24| |uif_ramif:219|lpm_bustri:26| |ramctrl16:231| |ramctrl16:231|busmux:33| |ramctrl16:231|busmux:33|lpm_mux:52| |ramctrl16:231|busmux:33|lpm_mux:52|altshift:external_latency_ffs| |ramctrl16:231|busmux:33|lpm_mux:52|muxlut:77| |ramctrl16:231|busmux:33|lpm_mux:52|muxlut:92| |ramctrl16:231|busmux:33|lpm_mux:52|muxlut:107| |ramctrl16:231|busmux:33|lpm_mux:52|muxlut:122| |ramctrl16:231|busmux:33|lpm_mux:52|muxlut:137| |ramctrl16:231|busmux:33|lpm_mux:52|muxlut:152| |ramctrl16:231|busmux:33|lpm_mux:52|muxlut:167| |ramctrl16:231|busmux:33|lpm_mux:52|muxlut:182| |pllunit_66:257| |pllunit_66:257|lpm_counter:4| |pllunit_66:257|lpm_counter:4|f8count:p8c0| |pllunit_66:257|lpm_counter:9| |pllunit_66:257|lpm_counter:9|lpm_add_sub:add_sub| |pllunit_66:257|lpm_counter:9|lpm_add_sub:add_sub|addcore:adder| |pllunit_66:257|lpm_counter:9|lpm_add_sub:add_sub|altshift:result_ext_latency_ffs| |pllunit_66:257|lpm_counter:9|lpm_add_sub:add_sub|altshift:carry_ext_latency_ffs| |pllunit_66:257|lpm_counter:9|lpm_add_sub:add_sub|altshift:oflow_ext_latency_ffs| |pllunit_66:257|lpm_counter:9|lpm_constant:scdw| |pllunit_66:257|lpm_counter:9|cmpconst:101| |pllunit_66:257|lpm_counter:5| |pllunit_66:257|lpm_counter:5|lpm_add_sub:add_sub| |pllunit_66:257|lpm_counter:5|lpm_add_sub:add_sub|addcore:adder| |pllunit_66:257|lpm_counter:5|lpm_add_sub:add_sub|altshift:result_ext_latency_ffs| |pllunit_66:257|lpm_counter:5|lpm_add_sub:add_sub|altshift:carry_ext_latency_ffs| |pllunit_66:257|lpm_counter:5|lpm_add_sub:add_sub|altshift:oflow_ext_latency_ffs| |pllunit_66:257|lpm_counter:5|lpm_constant:scdw| Device-Specific Information:c:\max2work\kumagai\univ_if\uifbase\uif10k_ramrw.rpt uif10k_ramrw ***** Logic for device 'uif10k_ramrw' compiled without errors. Device: EPF10K30AQC208-2 FLEX 10K Configuration Scheme: Passive Serial Device Options: User-Supplied Start-Up Clock = OFF Auto-Restart Configuration on Frame Error = OFF Release Clears Before Tri-States = OFF Enable Chip_Wide Reset = OFF Enable Chip-Wide Output Enable = OFF Enable INIT_DONE Output = ON JTAG User Code = 7f MultiVolt I/O = OFF Device-Specific Information:c:\max2work\kumagai\univ_if\uifbase\uif10k_ramrw.rpt uif10k_ramrw ** ERROR SUMMARY ** Info: Chip 'uif10k_ramrw' in device 'EPF10K30AQC208-2' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device E E R R R x x R R R R R R R R E E I E t t E I E E E E E E E E E S S I O S G G C C V S I O S S S S S S S x x E E G O V B G E N N l l C E V O C G E V E E E E E E t t R I R I I N I I I I I B C _ I I I I N I R D D o o C R I C I I C _ I I N I I I I R C R I R R I R R R I I V O V O O D O O O O O _ C D O O O O D O V I I c c I V O C O O _ D O O D O O O O V C V O V V O V V V O O E A E A A I A A A A A E I I B B B B I B E N N k k N E B I B B E I C C I C C C C E I E C E E C E E E 0 1 D 0 D 1 2 O 3 4 5 6 7 N O R 0 1 2 3 O 4 D T T 0 1 T D 5 O 6 7 N R 0 1 O 2 3 4 5 D O D 6 D D 7 D D D ----------------------------------------------------------------------------------------------------------_ / 208 206 204 202 200 198 196 194 192 190 188 186 184 182 180 178 176 174 172 170 168 166 164 162 160 158 |_ / 207 205 203 201 199 197 195 193 191 189 187 185 183 181 179 177 175 173 171 169 167 165 163 161 159 157 | #TCK | 1 156 | ^DATA0 ^CONF_DONE | 2 155 | ^DCLK ^nCEO | 3 154 | ^nCE #TDO | 4 153 | #TDI VCCIO | 5 152 | GNDIO VCCINT | 6 151 | GNDINT IOA_DIR | 7 150 | IOD_EN IOA_EN | 8 149 | IOD_DIR /IOCS0 | 9 148 | IOD0 RESERVED | 10 147 | IOD1 /IOCS1 | 11 146 | VCCIO /IOCS2 | 12 145 | VCCINT /IOCS3 | 13 144 | IOD2 /IOCS4 | 14 143 | IOD3 /IOCS5 | 15 142 | IOD4 RESERVED | 16 141 | IOD5 /IOCS6 | 17 140 | IOD6 /IOCS7 | 18 139 | IOD7 @INIT_DONE | 19 138 | VCCIO GNDIO | 20 137 | VCCINT GNDINT | 21 136 | IOE_EN VCCIO | 22 135 | IOE_DIR VCCINT | 23 134 | IOE0 TA16 | 24 133 | IOE1 TA15 | 25 132 | IOE2 TA14 | 26 131 | IOE3 TA13 | 27 EPF10K30AQC208-2 130 | GNDIO TA12 | 28 129 | GNDINT TA11 | 29 128 | IOE4 TA10 | 30 127 | IOE5 TA9 | 31 126 | IOE6 GNDIO | 32 125 | IOE7 GNDINT | 33 124 | GNDIO VCCIO | 34 123 | GNDINT VCCINT | 35 122 | IOF_EN TA8 | 36 121 | IOF_DIR TA7 | 37 120 | IOF0 TA6 | 38 119 | IOF1 TA5 | 39 118 | VCCIO TA4 | 40 117 | VCCINT TA3 | 41 116 | IOF2 VCCIO | 42 115 | IOF3 VCCINT | 43 114 | IOF4 TA2 | 44 113 | IOF5 TA1 | 45 112 | IOF6 TA0 | 46 111 | IOF7 /BHE | 47 110 | VCCIO GNDIO | 48 109 | VCCINT GNDINT | 49 108 | ^MSEL0 #TMS | 50 107 | ^MSEL1 #TRST | 51 106 | VCCINT ^nSTATUS | 52 105 | ^nCONFIG | 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 _| \ 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 | \----------------------------------------------------------------------------------------------------------- T T T T T T G T T T T T T V T T T T / G / / / V V / B G G G / V / I / / I I G I I / / / / V T / R R R R D D D D D D N D D D D D D C D D D D M N R M M C C T C N N N I C I O I I R R N R R I I I I C C T E E E E 0 1 2 3 4 5 D 6 7 8 9 1 1 C 1 1 1 1 E D O R W C C R L D D D O C O R O O Q Q D Q Q R R R R C L O S S S S I 0 1 I 2 3 4 5 M I M D R I I E K I I I R I W D R R 0 1 I 2 3 C C C C I K U E E E E O O C O C N N S N N N O Y R A O 0 1 2 3 O T R R R R S S T T E T T T E C V V V V T Q K E E E E D D D D N.C. = No Connect. This pin has no internal connection to the device. VCCINT = Dedicated power pin, which MUST be connected to VCC (3.3 volts). VCCIO = Dedicated power pin, which MUST be connected to VCC (3.3 volts). GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND. GNDIO = Dedicated ground pin, which MUST be connected to GND. RESERVED = Unused I/O pin, which MUST be left unconnected. ^ = Dedicated configuration pin. + = Reserved configuration pin, which is tri-stated during user mode. * = Reserved configuration pin, which drives out in user mode. PDn = Power Down pin. @ = Special-purpose pin. # = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use. & = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions. $ = Pin has PCI I/O option enabled. Pin is not '5.0 V'-tolerant. Device-Specific Information:c:\max2work\kumagai\univ_if\uifbase\uif10k_ramrw.rpt uif10k_ramrw ** RESOURCE USAGE ** Logic Column Row Array Interconnect Interconnect Clears/ External Block Logic Cells Driven Driven Clocks Presets Interconnect A15 8/ 8(100%) 3/ 8( 37%) 2/ 8( 25%) 2/2 0/2 7/22( 31%) A25 3/ 8( 37%) 3/ 8( 37%) 0/ 8( 0%) 1/2 0/2 4/22( 18%) A34 2/ 8( 25%) 2/ 8( 25%) 0/ 8( 0%) 1/2 0/2 3/22( 13%) B2 8/ 8(100%) 3/ 8( 37%) 2/ 8( 25%) 2/2 0/2 8/22( 36%) B6 8/ 8(100%) 3/ 8( 37%) 1/ 8( 12%) 2/2 0/2 8/22( 36%) B14 8/ 8(100%) 3/ 8( 37%) 1/ 8( 12%) 2/2 0/2 6/22( 27%) B21 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 2/22( 9%) B23 2/ 8( 25%) 2/ 8( 25%) 0/ 8( 0%) 1/2 0/2 3/22( 13%) B28 2/ 8( 25%) 2/ 8( 25%) 0/ 8( 0%) 1/2 0/2 3/22( 13%) B29 2/ 8( 25%) 2/ 8( 25%) 0/ 8( 0%) 1/2 0/2 3/22( 13%) B31 2/ 8( 25%) 2/ 8( 25%) 0/ 8( 0%) 1/2 0/2 3/22( 13%) B36 2/ 8( 25%) 2/ 8( 25%) 0/ 8( 0%) 1/2 0/2 3/22( 13%) C24 7/ 8( 87%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 0/22( 0%) C36 7/ 8( 87%) 1/ 8( 12%) 0/ 8( 0%) 2/2 0/2 1/22( 4%) D3 8/ 8(100%) 3/ 8( 37%) 2/ 8( 25%) 2/2 0/2 6/22( 27%) E7 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%) F3 6/ 8( 75%) 0/ 8( 0%) 3/ 8( 37%) 2/2 0/2 5/22( 22%) F11 8/ 8(100%) 4/ 8( 50%) 3/ 8( 37%) 2/2 0/2 5/22( 22%) F17 3/ 8( 37%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 1/22( 4%) F18 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 2/2 0/2 8/22( 36%) Embedded Column Row Array Embedded Interconnect Interconnect Read/ External Block Cells Driven Driven Clocks Write Interconnect Total dedicated input pins used: 4/6 ( 66%) Total I/O pins used: 124/141 ( 87%) Total logic cells used: 96/1728 ( 5%) Total embedded cells used: 0/48 ( 0%) Total EABs used: 0/6 ( 0%) Average fan-in: 2.21/4 ( 55%) Total fan-in: 213/6912 ( 3%) Total input pins required: 42 Total input I/O cell registers required: 0 Total output pins required: 20 Total output I/O cell registers required: 0 Total buried I/O cell registers required: 0 Total bidirectional pins required: 65 Total reserved pins required 1 Total logic cells required: 96 Total flipflops required: 86 Total packed registers required: 0 Total logic cells in carry chains: 0 Total number of carry chains: 0 Total logic cells in cascade chains: 0 Total number of cascade chains: 0 Total single-pin Clock Enables required: 0 Total single-pin Output Enables required: 0 Logic cells inserted for fitting: 1 Synthesized logic cells: 2/1728 ( 0%) Logic Cell and Embedded Cell Counts Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 EA 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Total(LC/EC) A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 0 0 0 0 0 0 0 0 3 0 0 0 0 0 0 0 0 2 0 0 13/0 B: 0 8 0 0 0 8 0 0 0 0 0 0 0 8 0 0 0 0 0 0 0 1 0 2 0 0 0 0 2 2 0 2 0 0 0 0 2 35/0 C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 0 0 0 0 0 0 0 0 0 0 0 7 14/0 D: 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8/0 E: 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1/0 F: 0 0 6 0 0 0 0 0 0 0 8 0 0 0 0 0 3 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 25/0 Total: 0 8 14 0 0 8 1 0 0 0 8 0 0 8 8 0 3 8 0 0 0 1 0 2 7 3 0 0 2 2 0 2 0 0 2 0 9 96/0 Device-Specific Information:c:\max2work\kumagai\univ_if\uifbase\uif10k_ramrw.rpt uif10k_ramrw ** INPUTS ** Fan-In Fan-Out Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name 79 - - - -- INPUT G 0 0 0 0 BCLK 47 - - F -- INPUT 0 0 0 0 /BHE 183 - - - -- INPUT G 0 0 0 0 ExtClock0 182 - - - -- INPUT 0 0 0 0 ExtClock1 205 - - - 34 BIDIR 0 0 0 0 IOA0 203 - - - 32 BIDIR 0 0 0 0 IOA1 202 - - - 31 BIDIR 0 0 0 0 IOA2 200 - - - 30 BIDIR 0 0 0 0 IOA3 199 - - - 29 BIDIR 0 0 0 0 IOA4 198 - - - 28 BIDIR 0 0 0 0 IOA5 197 - - - 28 BIDIR 0 0 0 0 IOA6 196 - - - 27 BIDIR 0 0 0 0 IOA7 192 - - - 24 BIDIR 0 0 0 0 IOB0 191 - - - 23 BIDIR 0 0 0 0 IOB1 190 - - - 22 BIDIR 0 0 0 0 IOB2 189 - - - 21 BIDIR 0 0 0 0 IOB3 187 - - - 20 BIDIR 0 0 0 0 IOB4 179 - - - 17 BIDIR 0 0 0 0 IOB5 177 - - - 16 BIDIR 0 0 0 0 IOB6 176 - - - 15 BIDIR 0 0 0 0 IOB7 9 - - A -- INPUT 0 0 0 0 /IOCS0 11 - - A -- INPUT 0 0 0 0 /IOCS1 12 - - B -- INPUT 0 0 0 0 /IOCS2 13 - - B -- INPUT 0 0 0 0 /IOCS3 14 - - B -- INPUT 0 0 0 0 /IOCS4 15 - - B -- INPUT 0 0 0 0 /IOCS5 17 - - C -- INPUT 0 0 0 0 /IOCS6 18 - - C -- INPUT 0 0 0 0 /IOCS7 173 - - - 13 BIDIR 0 0 0 0 IOC0 172 - - - 12 BIDIR 0 0 0 0 IOC1 170 - - - 11 BIDIR 0 0 0 0 IOC2 169 - - - 10 BIDIR 0 0 0 0 IOC3 168 - - - 09 BIDIR 0 0 0 0 IOC4 167 - - - 08 BIDIR 0 0 0 0 IOC5 163 - - - 06 BIDIR 0 0 0 0 IOC6 160 - - - 04 BIDIR 0 0 0 0 IOC7 148 - - A -- BIDIR 0 1 0 2 IOD0 147 - - A -- BIDIR 0 1 0 2 IOD1 144 - - B -- BIDIR 0 1 0 2 IOD2 143 - - B -- BIDIR 0 1 0 2 IOD3 142 - - B -- BIDIR 0 1 0 2 IOD4 141 - - B -- BIDIR 0 1 0 2 IOD5 140 - - B -- BIDIR 0 1 0 0 IOD6 139 - - B -- BIDIR 0 1 0 2 IOD7 134 - - C -- BIDIR 0 1 0 0 IOE0 133 - - C -- BIDIR 0 1 0 2 IOE1 132 - - C -- BIDIR 0 1 0 0 IOE2 131 - - C -- BIDIR 0 1 0 0 IOE3 128 - - D -- BIDIR 0 1 0 0 IOE4 127 - - D -- BIDIR 0 1 0 0 IOE5 126 - - D -- BIDIR 0 1 0 0 IOE6 125 - - D -- BIDIR 0 1 0 0 IOE7 120 - - E -- BIDIR 0 1 0 0 IOF0 119 - - E -- BIDIR 0 1 0 0 IOF1 116 - - F -- BIDIR 0 1 0 0 IOF2 115 - - F -- BIDIR 0 1 0 0 IOF3 114 - - F -- BIDIR 0 1 0 0 IOF4 113 - - F -- BIDIR 0 1 0 0 IOF5 112 - - F -- BIDIR 0 1 0 0 IOF6 111 - - F -- BIDIR 0 1 0 0 IOF7 83 - - - 17 INPUT 0 0 0 0 /IOR 88 - - - 14 INPUT 0 0 0 0 /IORACK 85 - - - 16 INPUT 0 0 0 4 /IOW 94 - - - 09 INPUT 0 0 0 0 /IRC0 95 - - - 09 INPUT 0 0 0 0 /IRC1 96 - - - 08 INPUT 0 0 0 0 /IRC2 97 - - - 07 INPUT 0 0 0 0 /IRC3 71 - - - 21 INPUT 0 0 0 0 /MEMCS 74 - - - 20 INPUT 0 0 0 0 /MRD 75 - - - 19 INPUT 0 0 0 0 /MWR 73 - - - 20 INPUT 0 0 0 0 /ROMCS 46 - - F -- INPUT 0 0 0 0 TA0 45 - - F -- INPUT 0 0 0 4 TA1 44 - - F -- INPUT 0 0 0 0 TA2 41 - - E -- INPUT 0 0 0 0 TA3 40 - - E -- INPUT 0 0 0 0 TA4 39 - - E -- INPUT 0 0 0 0 TA5 38 - - E -- INPUT 0 0 0 0 TA6 37 - - E -- INPUT 0 0 0 0 TA7 36 - - E -- INPUT 0 0 0 0 TA8 31 - - D -- INPUT 0 0 0 0 TA9 30 - - D -- INPUT 0 0 0 0 TA10 29 - - D -- INPUT 0 0 0 0 TA11 28 - - D -- INPUT 0 0 0 0 TA12 27 - - D -- INPUT 0 0 0 0 TA13 26 - - D -- INPUT 0 0 0 0 TA14 25 - - D -- INPUT 0 0 0 0 TA15 24 - - C -- INPUT 0 0 0 0 TA16 99 - - - 06 BIDIR 0 0 0 0 TCLK 53 - - - 36 BIDIR 0 1 0 2 TD0 54 - - - 35 BIDIR 0 1 0 2 TD1 55 - - - 34 BIDIR 0 1 0 2 TD2 56 - - - 33 BIDIR 0 1 0 2 TD3 57 - - - 32 BIDIR 0 1 0 2 TD4 58 - - - 31 BIDIR 0 1 0 2 TD5 60 - - - 30 BIDIR 0 1 0 2 TD6 61 - - - 29 BIDIR 0 1 0 2 TD7 62 - - - 28 BIDIR 0 1 0 2 TD8 63 - - - 27 BIDIR 0 1 0 2 TD9 64 - - - 26 BIDIR 0 1 0 2 TD10 65 - - - 26 BIDIR 0 1 0 2 TD11 67 - - - 25 BIDIR 0 1 0 2 TD12 68 - - - 24 BIDIR 0 1 0 2 TD13 69 - - - 23 BIDIR 0 1 0 2 TD14 70 - - - 22 BIDIR 0 1 0 1 TD15 100 - - - 05 INPUT 0 0 0 0 /TOUT 78 - - - -- INPUT 0 0 0 0 /TRESET Code: s = Synthesized pin or logic cell + = Synchronous flipflop / = Slow slew-rate output ! = NOT gate push-back r = Fitter-inserted logic cell * = PCI I/O is enabled @ = Uses single-pin Clock Enable & = Uses single-pin Output Enable G = Global Source. Fan-out destinations counted here do not include destinations that are driven using global routing resources. Refer to the Auto Global Signals, Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals Sections of this Report File for information on which signals' fan-outs are used as Clock, Clear, Preset, Output Enable, and synchronous Load signals. Device-Specific Information:c:\max2work\kumagai\univ_if\uifbase\uif10k_ramrw.rpt uif10k_ramrw ** OUTPUTS ** Fed By Fed By Fan-In Fan-Out Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name 208 - - - 36 OUTPUT 0 1 0 0 ExtIO0 207 - - - 35 OUTPUT 0 0 0 0 ExtIO1 7 - - A -- OUTPUT 0 0 0 0 IOA_DIR 8 - - A -- OUTPUT 0 0 0 0 IOA_EN 205 - - - 34 TRI 0 0 0 0 IOA0 203 - - - 32 TRI 0 0 0 0 IOA1 202 - - - 31 TRI 0 0 0 0 IOA2 200 - - - 30 TRI 0 0 0 0 IOA3 199 - - - 29 TRI 0 0 0 0 IOA4 198 - - - 28 TRI 0 0 0 0 IOA5 197 - - - 28 TRI 0 0 0 0 IOA6 196 - - - 27 TRI 0 0 0 0 IOA7 193 - - - 25 OUTPUT 0 0 0 0 IOB_DIR 195 - - - 26 OUTPUT 0 0 0 0 IOB_EN 192 - - - 24 TRI 0 0 0 0 IOB0 191 - - - 23 TRI 0 0 0 0 IOB1 190 - - - 22 TRI 0 0 0 0 IOB2 189 - - - 21 TRI 0 0 0 0 IOB3 187 - - - 20 TRI 0 0 0 0 IOB4 179 - - - 17 TRI 0 0 0 0 IOB5 177 - - - 16 TRI 0 0 0 0 IOB6 176 - - - 15 TRI 0 0 0 0 IOB7 174 - - - 14 OUTPUT 0 0 0 0 IOC_DIR 175 - - - 14 OUTPUT 0 0 0 0 IOC_EN 173 - - - 13 TRI 0 0 0 0 IOC0 172 - - - 12 TRI 0 0 0 0 IOC1 170 - - - 11 TRI 0 0 0 0 IOC2 169 - - - 10 TRI 0 0 0 0 IOC3 168 - - - 09 TRI 0 0 0 0 IOC4 167 - - - 08 TRI 0 0 0 0 IOC5 163 - - - 06 TRI 0 0 0 0 IOC6 160 - - - 04 TRI 0 0 0 0 IOC7 149 - - A -- OUTPUT 0 0 0 0 IOD_DIR 150 - - A -- OUTPUT 0 0 0 0 IOD_EN 148 - - A -- TRI 0 1 0 2 IOD0 147 - - A -- TRI 0 1 0 2 IOD1 144 - - B -- TRI 0 1 0 2 IOD2 143 - - B -- TRI 0 1 0 2 IOD3 142 - - B -- TRI 0 1 0 2 IOD4 141 - - B -- TRI 0 1 0 2 IOD5 140 - - B -- TRI 0 1 0 0 IOD6 139 - - B -- TRI 0 1 0 2 IOD7 135 - - C -- OUTPUT 0 0 0 0 IOE_DIR 136 - - C -- OUTPUT 0 0 0 0 IOE_EN 134 - - C -- TRI 0 1 0 0 IOE0 133 - - C -- TRI 0 1 0 2 IOE1 132 - - C -- TRI 0 1 0 0 IOE2 131 - - C -- TRI 0 1 0 0 IOE3 128 - - D -- TRI 0 1 0 0 IOE4 127 - - D -- TRI 0 1 0 0 IOE5 126 - - D -- TRI 0 1 0 0 IOE6 125 - - D -- TRI 0 1 0 0 IOE7 121 - - E -- OUTPUT 0 1 0 0 IOF_DIR 122 - - E -- OUTPUT 0 0 0 0 IOF_EN 120 - - E -- TRI 0 1 0 0 IOF0 119 - - E -- TRI 0 1 0 0 IOF1 116 - - F -- TRI 0 1 0 0 IOF2 115 - - F -- TRI 0 1 0 0 IOF3 114 - - F -- TRI 0 1 0 0 IOF4 113 - - F -- TRI 0 1 0 0 IOF5 112 - - F -- TRI 0 1 0 0 IOF6 111 - - F -- TRI 0 1 0 0 IOF7 86 - - - 15 OUTPUT 0 0 0 0 IORDY 87 - - - 14 OUTPUT 0 0 0 0 /IORREQ 89 - - - 13 OUTPUT 0 0 0 0 IRQ0 90 - - - 12 OUTPUT 0 0 0 0 IRQ1 92 - - - 11 OUTPUT 0 0 0 0 IRQ2 93 - - - 10 OUTPUT 0 0 0 0 IRQ3 99 - - - 06 TRI 0 0 0 0 TCLK 53 - - - 36 TRI 0 1 0 2 TD0 54 - - - 35 TRI 0 1 0 2 TD1 55 - - - 34 TRI 0 1 0 2 TD2 56 - - - 33 TRI 0 1 0 2 TD3 57 - - - 32 TRI 0 1 0 2 TD4 58 - - - 31 TRI 0 1 0 2 TD5 60 - - - 30 TRI 0 1 0 2 TD6 61 - - - 29 TRI 0 1 0 2 TD7 62 - - - 28 TRI 0 1 0 2 TD8 63 - - - 27 TRI 0 1 0 2 TD9 64 - - - 26 TRI 0 1 0 2 TD10 65 - - - 26 TRI 0 1 0 2 TD11 67 - - - 25 TRI 0 1 0 2 TD12 68 - - - 24 TRI 0 1 0 2 TD13 69 - - - 23 TRI 0 1 0 2 TD14 70 - - - 22 TRI 0 1 0 1 TD15 Code: s = Synthesized pin or logic cell + = Synchronous flipflop / = Slow slew-rate output ! = NOT gate push-back r = Fitter-inserted logic cell * = PCI I/O is enabled @ = Uses single-pin Clock Enable & = Uses single-pin Output Enable Device-Specific Information:c:\max2work\kumagai\univ_if\uifbase\uif10k_ramrw.rpt uif10k_ramrw ** BURIED LOGIC ** Fan-In Fan-Out IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name - 3 - E 07 SOFT s r 0 1 1 0 IOF_DIR~fit~in1 - 6 - C 36 DFFE + 0 3 0 1 |pllunit_66:257|LPM_COUNTER:4|f8count:p8c0|QD (|pllunit_66:257|LPM_COUNTER:4|f8count:p8c0|:5) - 4 - C 36 DFFE + 0 2 0 1 |pllunit_66:257|LPM_COUNTER:4|f8count:p8c0|QC (|pllunit_66:257|LPM_COUNTER:4|f8count:p8c0|:6) - 3 - C 36 DFFE + 0 1 0 2 |pllunit_66:257|LPM_COUNTER:4|f8count:p8c0|QB (|pllunit_66:257|LPM_COUNTER:4|f8count:p8c0|:7) - 2 - C 36 DFFE + 0 0 0 3 |pllunit_66:257|LPM_COUNTER:4|f8count:p8c0|QA (|pllunit_66:257|LPM_COUNTER:4|f8count:p8c0|:8) - 5 - C 36 DFFE + 0 1 0 1 |pllunit_66:257|LPM_COUNTER:5|dffs0 - 7 - C 36 DFFE + 0 2 0 1 |pllunit_66:257|LPM_COUNTER:5|dffs1 - 1 - C 24 AND2 0 3 0 4 |pllunit_66:257|LPM_COUNTER:9|cmpconst:101|and_cascade4 - 4 - C 24 DFFE + 0 0 0 3 |pllunit_66:257|LPM_COUNTER:9|dffs0 - 3 - C 24 DFFE + 0 2 0 2 |pllunit_66:257|LPM_COUNTER:9|dffs1 - 5 - C 24 DFFE + 0 3 0 1 |pllunit_66:257|LPM_COUNTER:9|dffs2 - 6 - C 24 DFFE + 0 1 0 2 |pllunit_66:257|LPM_COUNTER:9|dffs3 - 7 - C 24 DFFE + 0 2 0 1 |pllunit_66:257|LPM_COUNTER:9|dffs4 - 2 - C 24 AND2 0 3 0 3 |pllunit_66:257|LPM_COUNTER:9|lpm_add_sub:add_sub|addcore:adder|:63 - 1 - C 36 OR2 0 2 1 0 |pllunit_66:257|DiffOut (|pllunit_66:257|:6) - 5 - D 03 DFFE + 0 2 1 0 |ramctrl16:231|MA1 (|ramctrl16:231|~11~1) - 5 - B 14 DFFE + 0 2 1 0 |ramctrl16:231|MA2 (|ramctrl16:231|~11~2) - 1 - A 15 DFFE + 0 2 1 0 |ramctrl16:231|MA3 (|ramctrl16:231|~11~3) - 4 - F 03 DFFE + 0 2 1 0 |ramctrl16:231|MA4 (|ramctrl16:231|~11~4) - 5 - B 02 DFFE + 0 2 1 0 |ramctrl16:231|MA5 (|ramctrl16:231|~11~5) - 5 - F 03 DFFE + 0 2 1 0 |ramctrl16:231|MA6 (|ramctrl16:231|~11~6) - 2 - F 18 DFFE + 0 2 1 0 |ramctrl16:231|MA7 (|ramctrl16:231|~11~7) - 8 - B 06 DFFE + 0 2 1 0 |ramctrl16:231|MA8 (|ramctrl16:231|~11~8) - 8 - D 03 DFFE + 0 2 1 0 |ramctrl16:231|MA9 (|ramctrl16:231|~11~9) - 3 - B 06 DFFE + 0 2 1 0 |ramctrl16:231|MA10 (|ramctrl16:231|~11~10) - 1 - B 14 DFFE + 0 2 1 0 |ramctrl16:231|MA11 (|ramctrl16:231|~11~11) - 8 - B 14 DFFE + 0 2 1 0 |ramctrl16:231|MA12 (|ramctrl16:231|~11~12) - 4 - B 02 DFFE + 0 2 1 0 |ramctrl16:231|MA13 (|ramctrl16:231|~11~13) - 6 - B 14 DFFE + 0 2 1 0 |ramctrl16:231|MA14 (|ramctrl16:231|~11~14) - 8 - F 03 DFFE + 0 2 1 0 |ramctrl16:231|MA15 (|ramctrl16:231|~11~15) - 2 - A 15 DFFE + 0 1 0 2 |ramctrl16:231|Phase1 (|ramctrl16:231|:12) - 1 - D 03 DFFE + 0 2 0 1 |ramctrl16:231|D8 (|ramctrl16:231|~18~1) - 2 - B 06 DFFE + 0 2 0 1 |ramctrl16:231|D9 (|ramctrl16:231|~18~2) - 4 - A 15 DFFE + 0 2 0 1 |ramctrl16:231|D10 (|ramctrl16:231|~18~3) - 5 - A 15 DFFE + 0 2 0 1 |ramctrl16:231|D11 (|ramctrl16:231|~18~4) - 1 - B 02 DFFE + 0 2 0 1 |ramctrl16:231|D12 (|ramctrl16:231|~18~5) - 2 - B 02 DFFE + 0 2 0 1 |ramctrl16:231|D13 (|ramctrl16:231|~18~6) - 6 - F 18 DFFE + 0 2 0 1 |ramctrl16:231|D14 (|ramctrl16:231|~18~7) - 4 - B 06 DFFE + 0 2 0 1 |ramctrl16:231|D15 (|ramctrl16:231|~18~8) - 1 - B 36 DFFE + 0 2 1 0 |ramctrl16:231|DR0 (|ramctrl16:231|~19~1) - 5 - B 36 DFFE + 0 2 1 0 |ramctrl16:231|DR1 (|ramctrl16:231|~19~2) - 1 - A 34 DFFE + 0 2 1 0 |ramctrl16:231|DR2 (|ramctrl16:231|~19~3) - 4 - A 34 DFFE + 0 2 1 0 |ramctrl16:231|DR3 (|ramctrl16:231|~19~4) - 5 - B 31 DFFE + 0 2 1 0 |ramctrl16:231|DR4 (|ramctrl16:231|~19~5) - 1 - B 31 DFFE + 0 2 1 0 |ramctrl16:231|DR5 (|ramctrl16:231|~19~6) - 4 - B 29 DFFE + 0 2 1 0 |ramctrl16:231|DR6 (|ramctrl16:231|~19~7) - 1 - B 29 DFFE + 0 2 1 0 |ramctrl16:231|DR7 (|ramctrl16:231|~19~8) - 4 - F 18 AND2 s 0 2 0 1 |ramctrl16:231|Phase0~1 (|ramctrl16:231|~20~1) - 3 - F 18 AND2 0 4 0 27 |ramctrl16:231|Phase0 (|ramctrl16:231|:20) - 2 - D 03 DFFE + 0 1 0 3 |ramctrl16:231|Phase2 (|ramctrl16:231|:21) - 3 - D 03 DFFE + 0 1 0 12 |ramctrl16:231|Phase3 (|ramctrl16:231|:22) - 1 - F 11 DFFE + 0 3 0 1 |ramctrl16:231|DWE (|ramctrl16:231|:24) - 1 - F 18 DFFE + 0 1 0 1 |ramctrl16:231|:29 - 1 - B 28 DFFE + 0 2 1 0 |ramctrl16:231|DR8 (|ramctrl16:231|~32~1) - 4 - B 28 DFFE + 0 2 1 0 |ramctrl16:231|DR9 (|ramctrl16:231|~32~2) - 6 - A 25 DFFE + 0 2 1 0 |ramctrl16:231|DR10 (|ramctrl16:231|~32~3) - 4 - A 25 DFFE + 0 2 1 0 |ramctrl16:231|DR11 (|ramctrl16:231|~32~4) - 1 - A 25 DFFE + 0 2 1 0 |ramctrl16:231|DR12 (|ramctrl16:231|~32~5) - 1 - B 23 DFFE + 0 2 1 0 |ramctrl16:231|DR13 (|ramctrl16:231|~32~6) - 2 - B 23 DFFE + 0 2 1 0 |ramctrl16:231|DR14 (|ramctrl16:231|~32~7) - 5 - B 21 DFFE + 0 2 1 0 |ramctrl16:231|DR15 (|ramctrl16:231|~32~8) - 4 - D 03 DFFE + 0 4 1 0 |ramctrl16:231|MDW0 (|ramctrl16:231|~36~1) - 1 - B 06 DFFE + 0 4 1 0 |ramctrl16:231|MDW1 (|ramctrl16:231|~36~2) - 6 - A 15 DFFE + 0 4 1 0 |ramctrl16:231|MDW2 (|ramctrl16:231|~36~3) - 8 - A 15 DFFE + 0 4 1 0 |ramctrl16:231|MDW3 (|ramctrl16:231|~36~4) - 3 - B 02 DFFE + 0 4 1 0 |ramctrl16:231|MDW4 (|ramctrl16:231|~36~5) - 8 - B 02 DFFE + 0 4 1 0 |ramctrl16:231|MDW5 (|ramctrl16:231|~36~6) - 8 - F 18 DFFE + 0 4 1 0 |ramctrl16:231|MDW6 (|ramctrl16:231|~36~7) - 5 - B 06 DFFE + 0 4 1 0 |ramctrl16:231|MDW7 (|ramctrl16:231|~36~8) - 3 - A 15 OR2 0 2 0 8 |ramctrl16:231|:37 - 2 - F 17 DFFE + 0 1 0 2 |ramctrl16:231|Phase4 (|ramctrl16:231|:39) - 1 - F 17 DFFE + 0 1 0 4 |ramctrl16:231|Phase5 (|ramctrl16:231|:40) - 6 - F 17 DFFE + 0 3 1 0 |ramctrl16:231|MA0 (|ramctrl16:231|:43) - 3 - F 11 AND2 0 2 0 8 |ramctrl16:231|:47 - 7 - F 11 AND2 0 2 0 8 |ramctrl16:231|:48 - 8 - F 11 DFFE + 2 1 0 1 |ramctrl16:231|WREL (|ramctrl16:231|:52) - 6 - F 11 DFFE + 0 1 0 2 |ramctrl16:231|RDEL (|ramctrl16:231|:53) - 5 - F 18 DFFE + 0 1 0 2 Enable (:245) - 2 - F 11 DFFE + 2 1 0 1 :246 - 4 - F 11 AND2 2 0 0 15 :248 - 6 - D 03 DFFE + 0 2 0 1 MA0 (~250~1) - 7 - B 14 DFFE + 0 2 0 1 MA1 (~250~2) - 7 - A 15 DFFE + 0 2 0 1 MA2 (~250~3) - 1 - F 03 DFFE + 0 2 0 1 MA3 (~250~4) - 7 - B 02 DFFE + 0 2 0 1 MA4 (~250~5) - 2 - F 03 DFFE + 0 2 0 1 MA5 (~250~6) - 7 - F 18 DFFE + 0 2 0 1 MA6 (~250~7) - 7 - B 06 DFFE + 0 2 0 1 MA7 (~250~8) - 7 - D 03 DFFE + 0 2 0 1 MA8 (~250~9) - 6 - B 06 DFFE + 0 2 0 1 MA9 (~250~10) - 4 - B 14 DFFE + 0 2 0 1 MA10 (~250~11) - 3 - B 14 DFFE + 0 2 0 1 MA11 (~250~12) - 6 - B 02 DFFE + 0 2 0 1 MA12 (~250~13) - 2 - B 14 DFFE + 0 2 0 1 MA13 (~250~14) - 3 - F 03 DFFE + 0 2 0 1 MA14 (~250~15) - 5 - F 11 DFFE + 2 0 0 1 :253 Code: s = Synthesized pin or logic cell + = Synchronous flipflop / = Slow slew-rate output ! = NOT gate push-back r = Fitter-inserted logic cell * = PCI I/O is enabled p = Packed register Device-Specific Information:c:\max2work\kumagai\univ_if\uifbase\uif10k_ramrw.rpt uif10k_ramrw ** FASTTRACK INTERCONNECT UTILIZATION ** Row FastTrack Interconnect: Global Left Half- Right Half- FastTrack FastTrack FastTrack Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins A: 8/144( 5%) 5/ 72( 6%) 1/ 72( 1%) 2/16( 12%) 4/16( 25%) 2/16( 12%) B: 18/144( 12%) 10/ 72( 13%) 1/ 72( 1%) 4/16( 25%) 0/16( 0%) 6/16( 37%) C: 1/144( 0%) 4/ 72( 5%) 1/ 72( 1%) 3/16( 18%) 3/16( 18%) 4/16( 25%) D: 2/144( 1%) 8/ 72( 11%) 0/ 72( 0%) 7/16( 43%) 0/16( 0%) 4/16( 25%) E: 0/144( 0%) 4/ 72( 5%) 0/ 72( 0%) 6/16( 37%) 2/16( 12%) 2/16( 12%) F: 7/144( 4%) 14/ 72( 19%) 0/ 72( 0%) 4/16( 25%) 0/16( 0%) 6/16( 37%) Column FastTrack Interconnect: FastTrack Column Interconnect Input Pins Output Pins Bidir Pins 01: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 02: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 03: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 1/4( 25%) 05: 0/24( 0%) 1/4( 25%) 0/4( 0%) 0/4( 0%) 06: 3/24( 12%) 0/4( 0%) 0/4( 0%) 2/4( 50%) 07: 0/24( 0%) 1/4( 25%) 0/4( 0%) 0/4( 0%) 08: 0/24( 0%) 1/4( 25%) 0/4( 0%) 1/4( 25%) 09: 0/24( 0%) 2/4( 50%) 0/4( 0%) 1/4( 25%) 10: 0/24( 0%) 0/4( 0%) 1/4( 25%) 1/4( 25%) 11: 4/24( 16%) 0/4( 0%) 1/4( 25%) 1/4( 25%) 12: 0/24( 0%) 0/4( 0%) 1/4( 25%) 1/4( 25%) 13: 0/24( 0%) 0/4( 0%) 1/4( 25%) 1/4( 25%) 14: 3/24( 12%) 1/4( 25%) 3/4( 75%) 0/4( 0%) 15: 2/24( 8%) 0/4( 0%) 1/4( 25%) 1/4( 25%) 16: 2/24( 8%) 1/4( 25%) 0/4( 0%) 1/4( 25%) 17: 2/24( 8%) 1/4( 25%) 0/4( 0%) 1/4( 25%) 18: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 19: 0/24( 0%) 1/4( 25%) 0/4( 0%) 0/4( 0%) 20: 0/24( 0%) 2/4( 50%) 0/4( 0%) 1/4( 25%) 21: 0/24( 0%) 1/4( 25%) 0/4( 0%) 1/4( 25%) 22: 2/24( 8%) 0/4( 0%) 0/4( 0%) 2/4( 50%) 23: 2/24( 8%) 0/4( 0%) 0/4( 0%) 2/4( 50%) 24: 2/24( 8%) 0/4( 0%) 0/4( 0%) 2/4( 50%) 25: 2/24( 8%) 0/4( 0%) 1/4( 25%) 1/4( 25%) 26: 4/24( 16%) 0/4( 0%) 1/4( 25%) 2/4( 50%) 27: 3/24( 12%) 0/4( 0%) 0/4( 0%) 2/4( 50%) 28: 2/24( 8%) 0/4( 0%) 0/4( 0%) 3/4( 75%) 29: 3/24( 12%) 0/4( 0%) 0/4( 0%) 2/4( 50%) 30: 2/24( 8%) 0/4( 0%) 0/4( 0%) 2/4( 50%) 31: 2/24( 8%) 0/4( 0%) 0/4( 0%) 2/4( 50%) 32: 2/24( 8%) 0/4( 0%) 0/4( 0%) 2/4( 50%) 33: 2/24( 8%) 0/4( 0%) 0/4( 0%) 1/4( 25%) 34: 2/24( 8%) 0/4( 0%) 0/4( 0%) 2/4( 50%) 35: 2/24( 8%) 0/4( 0%) 1/4( 25%) 1/4( 25%) 36: 3/24( 12%) 0/4( 0%) 1/4( 25%) 1/4( 25%) EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) Device-Specific Information:c:\max2work\kumagai\univ_if\uifbase\uif10k_ramrw.rpt uif10k_ramrw ** CLOCK SIGNALS ** Type Fan-out Name INPUT 66 ExtClock0 INPUT 20 BCLK Device-Specific Information:c:\max2work\kumagai\univ_if\uifbase\uif10k_ramrw.rpt uif10k_ramrw ** EQUATIONS ** BCLK : INPUT; ExtClock0 : INPUT; ExtClock1 : INPUT; TA0 : INPUT; TA1 : INPUT; TA2 : INPUT; TA3 : INPUT; TA4 : INPUT; TA5 : INPUT; TA6 : INPUT; TA7 : INPUT; TA8 : INPUT; TA9 : INPUT; TA10 : INPUT; TA11 : INPUT; TA12 : INPUT; TA13 : INPUT; TA14 : INPUT; TA15 : INPUT; TA16 : INPUT; /BHE : INPUT; /IOCS0 : INPUT; /IOCS1 : INPUT; /IOCS2 : INPUT; /IOCS3 : INPUT; /IOCS4 : INPUT; /IOCS5 : INPUT; /IOCS6 : INPUT; /IOCS7 : INPUT; /IOR : INPUT; /IORACK : INPUT; /IOW : INPUT; /IRC0 : INPUT; /IRC1 : INPUT; /IRC2 : INPUT; /IRC3 : INPUT; /MEMCS : INPUT; /MRD : INPUT; /MWR : INPUT; /ROMCS : INPUT; /TOUT : INPUT; /TRESET : INPUT; -- Node name is ':245' = 'Enable' -- Equation name is 'Enable', location is LC5_F18, type is buried. Enable = DFFE( _LC2_F11, GLOBAL( ExtClock0), VCC, VCC, VCC); -- Node name is 'ExtIO0' -- Equation name is 'ExtIO0', type is output ExtIO0 = _LC1_C36; -- Node name is 'ExtIO1' -- Equation name is 'ExtIO1', type is output ExtIO1 = GND; -- Node name is 'IOA_DIR' -- Equation name is 'IOA_DIR', type is output IOA_DIR = GND; -- Node name is 'IOA_EN' -- Equation name is 'IOA_EN', type is output IOA_EN = GND; -- Node name is 'IOA0' -- Equation name is 'IOA0', type is bidir IOA0 = TRI(GND, GND); -- Node name is 'IOA1' -- Equation name is 'IOA1', type is bidir IOA1 = TRI(GND, GND); -- Node name is 'IOA2' -- Equation name is 'IOA2', type is bidir IOA2 = TRI(GND, GND); -- Node name is 'IOA3' -- Equation name is 'IOA3', type is bidir IOA3 = TRI(GND, GND); -- Node name is 'IOA4' -- Equation name is 'IOA4', type is bidir IOA4 = TRI(GND, GND); -- Node name is 'IOA5' -- Equation name is 'IOA5', type is bidir IOA5 = TRI(GND, GND); -- Node name is 'IOA6' -- Equation name is 'IOA6', type is bidir IOA6 = TRI(GND, GND); -- Node name is 'IOA7' -- Equation name is 'IOA7', type is bidir IOA7 = TRI(GND, GND); -- Node name is 'IOB_DIR' -- Equation name is 'IOB_DIR', type is output IOB_DIR = GND; -- Node name is 'IOB_EN' -- Equation name is 'IOB_EN', type is output IOB_EN = GND; -- Node name is 'IOB0' -- Equation name is 'IOB0', type is bidir IOB0 = TRI(GND, GND); -- Node name is 'IOB1' -- Equation name is 'IOB1', type is bidir IOB1 = TRI(GND, GND); -- Node name is 'IOB2' -- Equation name is 'IOB2', type is bidir IOB2 = TRI(GND, GND); -- Node name is 'IOB3' -- Equation name is 'IOB3', type is bidir IOB3 = TRI(GND, GND); -- Node name is 'IOB4' -- Equation name is 'IOB4', type is bidir IOB4 = TRI(GND, GND); -- Node name is 'IOB5' -- Equation name is 'IOB5', type is bidir IOB5 = TRI(GND, GND); -- Node name is 'IOB6' -- Equation name is 'IOB6', type is bidir IOB6 = TRI(GND, GND); -- Node name is 'IOB7' -- Equation name is 'IOB7', type is bidir IOB7 = TRI(GND, GND); -- Node name is 'IOC_DIR' -- Equation name is 'IOC_DIR', type is output IOC_DIR = GND; -- Node name is 'IOC_EN' -- Equation name is 'IOC_EN', type is output IOC_EN = GND; -- Node name is 'IOC0' -- Equation name is 'IOC0', type is bidir IOC0 = TRI(GND, GND); -- Node name is 'IOC1' -- Equation name is 'IOC1', type is bidir IOC1 = TRI(GND, GND); -- Node name is 'IOC2' -- Equation name is 'IOC2', type is bidir IOC2 = TRI(GND, GND); -- Node name is 'IOC3' -- Equation name is 'IOC3', type is bidir IOC3 = TRI(GND, GND); -- Node name is 'IOC4' -- Equation name is 'IOC4', type is bidir IOC4 = TRI(GND, GND); -- Node name is 'IOC5' -- Equation name is 'IOC5', type is bidir IOC5 = TRI(GND, GND); -- Node name is 'IOC6' -- Equation name is 'IOC6', type is bidir IOC6 = TRI(GND, GND); -- Node name is 'IOC7' -- Equation name is 'IOC7', type is bidir IOC7 = TRI(GND, GND); -- Node name is 'IOD_DIR' -- Equation name is 'IOD_DIR', type is output IOD_DIR = GND; -- Node name is 'IOD_EN' -- Equation name is 'IOD_EN', type is output IOD_EN = VCC; -- Node name is 'IOD0' -- Equation name is 'IOD0', type is bidir IOD0 = TRI(_LC6_A15, _LC1_F11); -- Node name is 'IOD1' -- Equation name is 'IOD1', type is bidir IOD1 = TRI(_LC8_A15, _LC1_F11); -- Node name is 'IOD2' -- Equation name is 'IOD2', type is bidir IOD2 = TRI(_LC1_B6, _LC1_F11); -- Node name is 'IOD3' -- Equation name is 'IOD3', type is bidir IOD3 = TRI(_LC3_B2, _LC1_F11); -- Node name is 'IOD4' -- Equation name is 'IOD4', type is bidir IOD4 = TRI(_LC4_D3, _LC1_F11); -- Node name is 'IOD5' -- Equation name is 'IOD5', type is bidir IOD5 = TRI(_LC8_B2, _LC1_F11); -- Node name is 'IOD6' -- Equation name is 'IOD6', type is bidir IOD6 = TRI(_LC6_B14, VCC); -- Node name is 'IOD7' -- Equation name is 'IOD7', type is bidir IOD7 = TRI(_LC8_F18, _LC1_F11); -- Node name is 'IOE_DIR' -- Equation name is 'IOE_DIR', type is output IOE_DIR = GND; -- Node name is 'IOE_EN' -- Equation name is 'IOE_EN', type is output IOE_EN = VCC; -- Node name is 'IOE0' -- Equation name is 'IOE0', type is bidir IOE0 = TRI(_LC4_B2, VCC); -- Node name is 'IOE1' -- Equation name is 'IOE1', type is bidir IOE1 = TRI(_LC5_B6, _LC1_F11); -- Node name is 'IOE2' -- Equation name is 'IOE2', type is bidir IOE2 = TRI(_LC6_F17, VCC); -- Node name is 'IOE3' -- Equation name is 'IOE3', type is bidir IOE3 = TRI(_LC8_B14, VCC); -- Node name is 'IOE4' -- Equation name is 'IOE4', type is bidir IOE4 = TRI(_LC1_B14, VCC); -- Node name is 'IOE5' -- Equation name is 'IOE5', type is bidir IOE5 = TRI(_LC3_B6, VCC); -- Node name is 'IOE6' -- Equation name is 'IOE6', type is bidir IOE6 = TRI(_LC5_D3, VCC); -- Node name is 'IOE7' -- Equation name is 'IOE7', type is bidir IOE7 = TRI(_LC8_D3, VCC); -- Node name is 'IOF_DIR' -- Equation name is 'IOF_DIR', type is output IOF_DIR = !_LC3_E7; -- Node name is 'IOF_DIR~fit~in1' -- Equation name is 'IOF_DIR~fit~in1', location is LC3_E7, type is buried. -- synthesized logic cell _LC3_E7 = LCELL( _LC1_F11); -- Node name is 'IOF_EN' -- Equation name is 'IOF_EN', type is output IOF_EN = VCC; -- Node name is 'IOF0' -- Equation name is 'IOF0', type is bidir IOF0 = TRI(_LC5_B14, VCC); -- Node name is 'IOF1' -- Equation name is 'IOF1', type is bidir IOF1 = TRI(_LC8_B6, VCC); -- Node name is 'IOF2' -- Equation name is 'IOF2', type is bidir IOF2 = TRI(_LC1_A15, VCC); -- Node name is 'IOF3' -- Equation name is 'IOF3', type is bidir IOF3 = TRI(_LC2_F18, VCC); -- Node name is 'IOF4' -- Equation name is 'IOF4', type is bidir IOF4 = TRI(_LC4_F3, VCC); -- Node name is 'IOF5' -- Equation name is 'IOF5', type is bidir IOF5 = TRI(_LC5_F3, VCC); -- Node name is 'IOF6' -- Equation name is 'IOF6', type is bidir IOF6 = TRI(_LC5_B2, VCC); -- Node name is 'IOF7' -- Equation name is 'IOF7', type is bidir IOF7 = TRI(_LC8_F3, VCC); -- Node name is 'IORDY' -- Equation name is 'IORDY', type is output IORDY = VCC; -- Node name is 'IRQ0' -- Equation name is 'IRQ0', type is output IRQ0 = GND; -- Node name is 'IRQ1' -- Equation name is 'IRQ1', type is output IRQ1 = GND; -- Node name is 'IRQ2' -- Equation name is 'IRQ2', type is output IRQ2 = GND; -- Node name is 'IRQ3' -- Equation name is 'IRQ3', type is output IRQ3 = GND; -- Node name is '~250~1' = 'MA0' -- Equation name is '~250~1', location is LC6_D3, type is buried. MA0 = DFFE( TD0, GLOBAL( BCLK), VCC, VCC, _LC4_F11); -- Node name is '~250~2' = 'MA1' -- Equation name is '~250~2', location is LC7_B14, type is buried. MA1 = DFFE( TD1, GLOBAL( BCLK), VCC, VCC, _LC4_F11); -- Node name is '~250~3' = 'MA2' -- Equation name is '~250~3', location is LC7_A15, type is buried. MA2 = DFFE( TD2, GLOBAL( BCLK), VCC, VCC, _LC4_F11); -- Node name is '~250~4' = 'MA3' -- Equation name is '~250~4', location is LC1_F3, type is buried. MA3 = DFFE( TD3, GLOBAL( BCLK), VCC, VCC, _LC4_F11); -- Node name is '~250~5' = 'MA4' -- Equation name is '~250~5', location is LC7_B2, type is buried. MA4 = DFFE( TD4, GLOBAL( BCLK), VCC, VCC, _LC4_F11); -- Node name is '~250~6' = 'MA5' -- Equation name is '~250~6', location is LC2_F3, type is buried. MA5 = DFFE( TD5, GLOBAL( BCLK), VCC, VCC, _LC4_F11); -- Node name is '~250~7' = 'MA6' -- Equation name is '~250~7', location is LC7_F18, type is buried. MA6 = DFFE( TD6, GLOBAL( BCLK), VCC, VCC, _LC4_F11); -- Node name is '~250~8' = 'MA7' -- Equation name is '~250~8', location is LC7_B6, type is buried. MA7 = DFFE( TD7, GLOBAL( BCLK), VCC, VCC, _LC4_F11); -- Node name is '~250~9' = 'MA8' -- Equation name is '~250~9', location is LC7_D3, type is buried. MA8 = DFFE( TD8, GLOBAL( BCLK), VCC, VCC, _LC4_F11); -- Node name is '~250~10' = 'MA9' -- Equation name is '~250~10', location is LC6_B6, type is buried. MA9 = DFFE( TD9, GLOBAL( BCLK), VCC, VCC, _LC4_F11); -- Node name is '~250~11' = 'MA10' -- Equation name is '~250~11', location is LC4_B14, type is buried. MA10 = DFFE( TD10, GLOBAL( BCLK), VCC, VCC, _LC4_F11); -- Node name is '~250~12' = 'MA11' -- Equation name is '~250~12', location is LC3_B14, type is buried. MA11 = DFFE( TD11, GLOBAL( BCLK), VCC, VCC, _LC4_F11); -- Node name is '~250~13' = 'MA12' -- Equation name is '~250~13', location is LC6_B2, type is buried. MA12 = DFFE( TD12, GLOBAL( BCLK), VCC, VCC, _LC4_F11); -- Node name is '~250~14' = 'MA13' -- Equation name is '~250~14', location is LC2_B14, type is buried. MA13 = DFFE( TD13, GLOBAL( BCLK), VCC, VCC, _LC4_F11); -- Node name is '~250~15' = 'MA14' -- Equation name is '~250~15', location is LC3_F3, type is buried. MA14 = DFFE( TD14, GLOBAL( BCLK), VCC, VCC, _LC4_F11); -- Node name is 'TCLK' -- Equation name is 'TCLK', type is bidir TCLK = TRI(GND, GND); -- Node name is 'TD0' -- Equation name is 'TD0', type is bidir TD0 = TRI(_LC1_B36, !/IOCS2); -- Node name is 'TD1' -- Equation name is 'TD1', type is bidir TD1 = TRI(_LC5_B36, !/IOCS2); -- Node name is 'TD2' -- Equation name is 'TD2', type is bidir TD2 = TRI(_LC1_A34, !/IOCS2); -- Node name is 'TD3' -- Equation name is 'TD3', type is bidir TD3 = TRI(_LC4_A34, !/IOCS2); -- Node name is 'TD4' -- Equation name is 'TD4', type is bidir TD4 = TRI(_LC5_B31, !/IOCS2); -- Node name is 'TD5' -- Equation name is 'TD5', type is bidir TD5 = TRI(_LC1_B31, !/IOCS2); -- Node name is 'TD6' -- Equation name is 'TD6', type is bidir TD6 = TRI(_LC4_B29, !/IOCS2); -- Node name is 'TD7' -- Equation name is 'TD7', type is bidir TD7 = TRI(_LC1_B29, !/IOCS2); -- Node name is 'TD8' -- Equation name is 'TD8', type is bidir TD8 = TRI(_LC1_B28, !/IOCS2); -- Node name is 'TD9' -- Equation name is 'TD9', type is bidir TD9 = TRI(_LC4_B28, !/IOCS2); -- Node name is 'TD10' -- Equation name is 'TD10', type is bidir TD10 = TRI(_LC6_A25, !/IOCS2); -- Node name is 'TD11' -- Equation name is 'TD11', type is bidir TD11 = TRI(_LC4_A25, !/IOCS2); -- Node name is 'TD12' -- Equation name is 'TD12', type is bidir TD12 = TRI(_LC1_A25, !/IOCS2); -- Node name is 'TD13' -- Equation name is 'TD13', type is bidir TD13 = TRI(_LC1_B23, !/IOCS2); -- Node name is 'TD14' -- Equation name is 'TD14', type is bidir TD14 = TRI(_LC2_B23, !/IOCS2); -- Node name is 'TD15' -- Equation name is 'TD15', type is bidir TD15 = TRI(_LC5_B21, !/IOCS2); -- Node name is '|pllunit_66:257|:6' = '|pllunit_66:257|DiffOut' -- Equation name is '_LC1_C36', type is buried _LC1_C36 = LCELL( _EQ001); _EQ001 = !_LC6_C36 & _LC7_C36 # _LC6_C36 & !_LC7_C36; -- Node name is '|pllunit_66:257|LPM_COUNTER:4|f8count:p8c0|:8' = '|pllunit_66:257|LPM_COUNTER:4|f8count:p8c0|QA' -- Equation name is '_LC2_C36', type is buried _LC2_C36 = DFFE(!_LC2_C36, GLOBAL( BCLK), VCC, VCC, VCC); -- Node name is '|pllunit_66:257|LPM_COUNTER:4|f8count:p8c0|:7' = '|pllunit_66:257|LPM_COUNTER:4|f8count:p8c0|QB' -- Equation name is '_LC3_C36', type is buried _LC3_C36 = DFFE( _EQ002, GLOBAL( BCLK), VCC, VCC, VCC); _EQ002 = _LC2_C36 & !_LC3_C36 # !_LC2_C36 & _LC3_C36; -- Node name is '|pllunit_66:257|LPM_COUNTER:4|f8count:p8c0|:6' = '|pllunit_66:257|LPM_COUNTER:4|f8count:p8c0|QC' -- Equation name is '_LC4_C36', type is buried _LC4_C36 = DFFE( _EQ003, GLOBAL( BCLK), VCC, VCC, VCC); _EQ003 = !_LC2_C36 & _LC4_C36 # !_LC3_C36 & _LC4_C36 # _LC2_C36 & _LC3_C36 & !_LC4_C36; -- Node name is '|pllunit_66:257|LPM_COUNTER:4|f8count:p8c0|:5' = '|pllunit_66:257|LPM_COUNTER:4|f8count:p8c0|QD' -- Equation name is '_LC6_C36', type is buried _LC6_C36 = DFFE( _EQ004, GLOBAL( BCLK), VCC, VCC, VCC); _EQ004 = !_LC2_C36 & _LC6_C36 # !_LC3_C36 & _LC6_C36 # !_LC4_C36 & _LC6_C36 # _LC2_C36 & _LC3_C36 & _LC4_C36 & !_LC6_C36; -- Node name is '|pllunit_66:257|LPM_COUNTER:5|dffs0' from file "lpm_counter.tdf" line 234, column 10 -- Equation name is '_LC5_C36', type is buried _LC5_C36 = DFFE(!_LC5_C36, GLOBAL( ExtClock0), VCC, VCC, _LC1_C24); -- Node name is '|pllunit_66:257|LPM_COUNTER:5|dffs1' from file "lpm_counter.tdf" line 234, column 10 -- Equation name is '_LC7_C36', type is buried _LC7_C36 = DFFE( _EQ005, GLOBAL( ExtClock0), VCC, VCC, _LC1_C24); _EQ005 = !_LC5_C36 & _LC7_C36 # _LC5_C36 & !_LC7_C36; -- Node name is '|pllunit_66:257|LPM_COUNTER:9|cmpconst:101|and_cascade4' from file "cmpconst.tdf" line 58, column 37 -- Equation name is '_LC1_C24', type is buried _LC1_C24 = LCELL( _EQ006); _EQ006 = _LC2_C24 & _LC6_C24 & !_LC7_C24; -- Node name is '|pllunit_66:257|LPM_COUNTER:9|dffs0' from file "lpm_counter.tdf" line 234, column 10 -- Equation name is '_LC4_C24', type is buried _LC4_C24 = DFFE(!_LC4_C24, GLOBAL( ExtClock0), VCC, VCC, VCC); -- Node name is '|pllunit_66:257|LPM_COUNTER:9|dffs1' from file "lpm_counter.tdf" line 234, column 10 -- Equation name is '_LC3_C24', type is buried _LC3_C24 = DFFE( _EQ007, GLOBAL( ExtClock0), VCC, VCC, VCC); _EQ007 = !_LC1_C24 & !_LC3_C24 & _LC4_C24 # !_LC1_C24 & _LC3_C24 & !_LC4_C24; -- Node name is '|pllunit_66:257|LPM_COUNTER:9|dffs2' from file "lpm_counter.tdf" line 234, column 10 -- Equation name is '_LC5_C24', type is buried _LC5_C24 = DFFE( _EQ008, GLOBAL( ExtClock0), VCC, VCC, VCC); _EQ008 = !_LC1_C24 & !_LC4_C24 & _LC5_C24 # !_LC1_C24 & !_LC3_C24 & _LC5_C24 # !_LC1_C24 & _LC3_C24 & _LC4_C24 & !_LC5_C24; -- Node name is '|pllunit_66:257|LPM_COUNTER:9|dffs3' from file "lpm_counter.tdf" line 234, column 10 -- Equation name is '_LC6_C24', type is buried _LC6_C24 = DFFE( _EQ009, GLOBAL( ExtClock0), VCC, VCC, VCC); _EQ009 = !_LC2_C24 & _LC6_C24 # _LC2_C24 & !_LC6_C24; -- Node name is '|pllunit_66:257|LPM_COUNTER:9|dffs4' from file "lpm_counter.tdf" line 234, column 10 -- Equation name is '_LC7_C24', type is buried _LC7_C24 = DFFE( _EQ010, GLOBAL( ExtClock0), VCC, VCC, VCC); _EQ010 = !_LC6_C24 & _LC7_C24 # !_LC2_C24 & _LC7_C24; -- Node name is '|pllunit_66:257|LPM_COUNTER:9|lpm_add_sub:add_sub|addcore:adder|:63' from file "addcore.tdf" line 312, column 64 -- Equation name is '_LC2_C24', type is buried _LC2_C24 = LCELL( _EQ011); _EQ011 = _LC3_C24 & _LC4_C24 & _LC5_C24; -- Node name is '|ramctrl16:231|~19~1' = '|ramctrl16:231|DR0' -- Equation name is '_LC1_B36', type is buried _LC1_B36 = DFFE( IOD4, GLOBAL( ExtClock0), VCC, VCC, _LC3_F11); -- Node name is '|ramctrl16:231|~19~2' = '|ramctrl16:231|DR1' -- Equation name is '_LC5_B36', type is buried _LC5_B36 = DFFE( IOD2, GLOBAL( ExtClock0), VCC, VCC, _LC3_F11); -- Node name is '|ramctrl16:231|~19~3' = '|ramctrl16:231|DR2' -- Equation name is '_LC1_A34', type is buried _LC1_A34 = DFFE( IOD0, GLOBAL( ExtClock0), VCC, VCC, _LC3_F11); -- Node name is '|ramctrl16:231|~19~4' = '|ramctrl16:231|DR3' -- Equation name is '_LC4_A34', type is buried _LC4_A34 = DFFE( IOD1, GLOBAL( ExtClock0), VCC, VCC, _LC3_F11); -- Node name is '|ramctrl16:231|~19~5' = '|ramctrl16:231|DR4' -- Equation name is '_LC5_B31', type is buried _LC5_B31 = DFFE( IOD3, GLOBAL( ExtClock0), VCC, VCC, _LC3_F11); -- Node name is '|ramctrl16:231|~19~6' = '|ramctrl16:231|DR5' -- Equation name is '_LC1_B31', type is buried _LC1_B31 = DFFE( IOD5, GLOBAL( ExtClock0), VCC, VCC, _LC3_F11); -- Node name is '|ramctrl16:231|~19~7' = '|ramctrl16:231|DR6' -- Equation name is '_LC4_B29', type is buried _LC4_B29 = DFFE( IOD7, GLOBAL( ExtClock0), VCC, VCC, _LC3_F11); -- Node name is '|ramctrl16:231|~19~8' = '|ramctrl16:231|DR7' -- Equation name is '_LC1_B29', type is buried _LC1_B29 = DFFE( IOE1, GLOBAL( ExtClock0), VCC, VCC, _LC3_F11); -- Node name is '|ramctrl16:231|~32~1' = '|ramctrl16:231|DR8' -- Equation name is '_LC1_B28', type is buried _LC1_B28 = DFFE( IOD4, GLOBAL( ExtClock0), VCC, VCC, _LC7_F11); -- Node name is '|ramctrl16:231|~32~2' = '|ramctrl16:231|DR9' -- Equation name is '_LC4_B28', type is buried _LC4_B28 = DFFE( IOD2, GLOBAL( ExtClock0), VCC, VCC, _LC7_F11); -- Node name is '|ramctrl16:231|~32~3' = '|ramctrl16:231|DR10' -- Equation name is '_LC6_A25', type is buried _LC6_A25 = DFFE( IOD0, GLOBAL( ExtClock0), VCC, VCC, _LC7_F11); -- Node name is '|ramctrl16:231|~32~4' = '|ramctrl16:231|DR11' -- Equation name is '_LC4_A25', type is buried _LC4_A25 = DFFE( IOD1, GLOBAL( ExtClock0), VCC, VCC, _LC7_F11); -- Node name is '|ramctrl16:231|~32~5' = '|ramctrl16:231|DR12' -- Equation name is '_LC1_A25', type is buried _LC1_A25 = DFFE( IOD3, GLOBAL( ExtClock0), VCC, VCC, _LC7_F11); -- Node name is '|ramctrl16:231|~32~6' = '|ramctrl16:231|DR13' -- Equation name is '_LC1_B23', type is buried _LC1_B23 = DFFE( IOD5, GLOBAL( ExtClock0), VCC, VCC, _LC7_F11); -- Node name is '|ramctrl16:231|~32~7' = '|ramctrl16:231|DR14' -- Equation name is '_LC2_B23', type is buried _LC2_B23 = DFFE( IOD7, GLOBAL( ExtClock0), VCC, VCC, _LC7_F11); -- Node name is '|ramctrl16:231|~32~8' = '|ramctrl16:231|DR15' -- Equation name is '_LC5_B21', type is buried _LC5_B21 = DFFE( IOE1, GLOBAL( ExtClock0), VCC, VCC, _LC7_F11); -- Node name is '|ramctrl16:231|:24' = '|ramctrl16:231|DWE' -- Equation name is '_LC1_F11', type is buried _LC1_F11 = DFFE( _EQ012, GLOBAL( ExtClock0), VCC, VCC, VCC); _EQ012 = _LC1_F17 & _LC8_F11 # _LC2_D3 & _LC8_F11; -- Node name is '|ramctrl16:231|~18~1' = '|ramctrl16:231|D8' -- Equation name is '_LC1_D3', type is buried _LC1_D3 = DFFE( TD8, GLOBAL( ExtClock0), VCC, VCC, _LC3_F18); -- Node name is '|ramctrl16:231|~18~2' = '|ramctrl16:231|D9' -- Equation name is '_LC2_B6', type is buried _LC2_B6 = DFFE( TD9, GLOBAL( ExtClock0), VCC, VCC, _LC3_F18); -- Node name is '|ramctrl16:231|~18~3' = '|ramctrl16:231|D10' -- Equation name is '_LC4_A15', type is buried _LC4_A15 = DFFE( TD10, GLOBAL( ExtClock0), VCC, VCC, _LC3_F18); -- Node name is '|ramctrl16:231|~18~4' = '|ramctrl16:231|D11' -- Equation name is '_LC5_A15', type is buried _LC5_A15 = DFFE( TD11, GLOBAL( ExtClock0), VCC, VCC, _LC3_F18); -- Node name is '|ramctrl16:231|~18~5' = '|ramctrl16:231|D12' -- Equation name is '_LC1_B2', type is buried _LC1_B2 = DFFE( TD12, GLOBAL( ExtClock0), VCC, VCC, _LC3_F18); -- Node name is '|ramctrl16:231|~18~6' = '|ramctrl16:231|D13' -- Equation name is '_LC2_B2', type is buried _LC2_B2 = DFFE( TD13, GLOBAL( ExtClock0), VCC, VCC, _LC3_F18); -- Node name is '|ramctrl16:231|~18~7' = '|ramctrl16:231|D14' -- Equation name is '_LC6_F18', type is buried _LC6_F18 = DFFE( TD14, GLOBAL( ExtClock0), VCC, VCC, _LC3_F18); -- Node name is '|ramctrl16:231|~18~8' = '|ramctrl16:231|D15' -- Equation name is '_LC4_B6', type is buried _LC4_B6 = DFFE( TD15, GLOBAL( ExtClock0), VCC, VCC, _LC3_F18); -- Node name is '|ramctrl16:231|:43' = '|ramctrl16:231|MA0' -- Equation name is '_LC6_F17', type is buried _LC6_F17 = DFFE( _EQ013, GLOBAL( ExtClock0), VCC, VCC, VCC); _EQ013 = _LC1_F17 # _LC3_D3 # _LC2_F17; -- Node name is '|ramctrl16:231|~11~1' = '|ramctrl16:231|MA1' -- Equation name is '_LC5_D3', type is buried _LC5_D3 = DFFE( MA0, GLOBAL( ExtClock0), VCC, VCC, _LC3_F18); -- Node name is '|ramctrl16:231|~11~2' = '|ramctrl16:231|MA2' -- Equation name is '_LC5_B14', type is buried _LC5_B14 = DFFE( MA1, GLOBAL( ExtClock0), VCC, VCC, _LC3_F18); -- Node name is '|ramctrl16:231|~11~3' = '|ramctrl16:231|MA3' -- Equation name is '_LC1_A15', type is buried _LC1_A15 = DFFE( MA2, GLOBAL( ExtClock0), VCC, VCC, _LC3_F18); -- Node name is '|ramctrl16:231|~11~4' = '|ramctrl16:231|MA4' -- Equation name is '_LC4_F3', type is buried _LC4_F3 = DFFE( MA3, GLOBAL( ExtClock0), VCC, VCC, _LC3_F18); -- Node name is '|ramctrl16:231|~11~5' = '|ramctrl16:231|MA5' -- Equation name is '_LC5_B2', type is buried _LC5_B2 = DFFE( MA4, GLOBAL( ExtClock0), VCC, VCC, _LC3_F18); -- Node name is '|ramctrl16:231|~11~6' = '|ramctrl16:231|MA6' -- Equation name is '_LC5_F3', type is buried _LC5_F3 = DFFE( MA5, GLOBAL( ExtClock0), VCC, VCC, _LC3_F18); -- Node name is '|ramctrl16:231|~11~7' = '|ramctrl16:231|MA7' -- Equation name is '_LC2_F18', type is buried _LC2_F18 = DFFE( MA6, GLOBAL( ExtClock0), VCC, VCC, _LC3_F18); -- Node name is '|ramctrl16:231|~11~8' = '|ramctrl16:231|MA8' -- Equation name is '_LC8_B6', type is buried _LC8_B6 = DFFE( MA7, GLOBAL( ExtClock0), VCC, VCC, _LC3_F18); -- Node name is '|ramctrl16:231|~11~9' = '|ramctrl16:231|MA9' -- Equation name is '_LC8_D3', type is buried _LC8_D3 = DFFE( MA8, GLOBAL( ExtClock0), VCC, VCC, _LC3_F18); -- Node name is '|ramctrl16:231|~11~10' = '|ramctrl16:231|MA10' -- Equation name is '_LC3_B6', type is buried _LC3_B6 = DFFE( MA9, GLOBAL( ExtClock0), VCC, VCC, _LC3_F18); -- Node name is '|ramctrl16:231|~11~11' = '|ramctrl16:231|MA11' -- Equation name is '_LC1_B14', type is buried _LC1_B14 = DFFE( MA10, GLOBAL( ExtClock0), VCC, VCC, _LC3_F18); -- Node name is '|ramctrl16:231|~11~12' = '|ramctrl16:231|MA12' -- Equation name is '_LC8_B14', type is buried _LC8_B14 = DFFE( MA11, GLOBAL( ExtClock0), VCC, VCC, _LC3_F18); -- Node name is '|ramctrl16:231|~11~13' = '|ramctrl16:231|MA13' -- Equation name is '_LC4_B2', type is buried _LC4_B2 = DFFE( MA12, GLOBAL( ExtClock0), VCC, VCC, _LC3_F18); -- Node name is '|ramctrl16:231|~11~14' = '|ramctrl16:231|MA14' -- Equation name is '_LC6_B14', type is buried _LC6_B14 = DFFE( MA13, GLOBAL( ExtClock0), VCC, VCC, _LC3_F18); -- Node name is '|ramctrl16:231|~11~15' = '|ramctrl16:231|MA15' -- Equation name is '_LC8_F3', type is buried _LC8_F3 = DFFE( MA14, GLOBAL( ExtClock0), VCC, VCC, _LC3_F18); -- Node name is '|ramctrl16:231|~36~1' = '|ramctrl16:231|MDW0' -- Equation name is '_LC4_D3', type is buried _LC4_D3 = DFFE( _EQ014, GLOBAL( ExtClock0), VCC, VCC, _LC3_A15); _EQ014 = !_LC3_D3 & TD0 # _LC1_D3 & _LC3_D3; -- Node name is '|ramctrl16:231|~36~2' = '|ramctrl16:231|MDW1' -- Equation name is '_LC1_B6', type is buried _LC1_B6 = DFFE( _EQ015, GLOBAL( ExtClock0), VCC, VCC, _LC3_A15); _EQ015 = !_LC3_D3 & TD1 # _LC2_B6 & _LC3_D3; -- Node name is '|ramctrl16:231|~36~3' = '|ramctrl16:231|MDW2' -- Equation name is '_LC6_A15', type is buried _LC6_A15 = DFFE( _EQ016, GLOBAL( ExtClock0), VCC, VCC, _LC3_A15); _EQ016 = !_LC3_D3 & TD2 # _LC3_D3 & _LC4_A15; -- Node name is '|ramctrl16:231|~36~4' = '|ramctrl16:231|MDW3' -- Equation name is '_LC8_A15', type is buried _LC8_A15 = DFFE( _EQ017, GLOBAL( ExtClock0), VCC, VCC, _LC3_A15); _EQ017 = !_LC3_D3 & TD3 # _LC3_D3 & _LC5_A15; -- Node name is '|ramctrl16:231|~36~5' = '|ramctrl16:231|MDW4' -- Equation name is '_LC3_B2', type is buried _LC3_B2 = DFFE( _EQ018, GLOBAL( ExtClock0), VCC, VCC, _LC3_A15); _EQ018 = !_LC3_D3 & TD4 # _LC1_B2 & _LC3_D3; -- Node name is '|ramctrl16:231|~36~6' = '|ramctrl16:231|MDW5' -- Equation name is '_LC8_B2', type is buried _LC8_B2 = DFFE( _EQ019, GLOBAL( ExtClock0), VCC, VCC, _LC3_A15); _EQ019 = !_LC3_D3 & TD5 # _LC2_B2 & _LC3_D3; -- Node name is '|ramctrl16:231|~36~7' = '|ramctrl16:231|MDW6' -- Equation name is '_LC8_F18', type is buried _LC8_F18 = DFFE( _EQ020, GLOBAL( ExtClock0), VCC, VCC, _LC3_A15); _EQ020 = !_LC3_D3 & TD6 # _LC3_D3 & _LC6_F18; -- Node name is '|ramctrl16:231|~36~8' = '|ramctrl16:231|MDW7' -- Equation name is '_LC5_B6', type is buried _LC5_B6 = DFFE( _EQ021, GLOBAL( ExtClock0), VCC, VCC, _LC3_A15); _EQ021 = !_LC3_D3 & TD7 # _LC3_D3 & _LC4_B6; -- Node name is '|ramctrl16:231|~20~1' = '|ramctrl16:231|Phase0~1' -- Equation name is '_LC4_F18', type is buried -- synthesized logic cell _LC4_F18 = LCELL( _EQ022); _EQ022 = !_LC1_F17 & !_LC3_D3; -- Node name is '|ramctrl16:231|:20' = '|ramctrl16:231|Phase0' -- Equation name is '_LC3_F18', type is buried _LC3_F18 = LCELL( _EQ023); _EQ023 = Enable & !_LC1_F18 & !_LC2_A15 & _LC4_F18; -- Node name is '|ramctrl16:231|:12' = '|ramctrl16:231|Phase1' -- Equation name is '_LC2_A15', type is buried _LC2_A15 = DFFE( _LC3_F18, GLOBAL( ExtClock0), VCC, VCC, VCC); -- Node name is '|ramctrl16:231|:21' = '|ramctrl16:231|Phase2' -- Equation name is '_LC2_D3', type is buried _LC2_D3 = DFFE( _LC2_A15, GLOBAL( ExtClock0), VCC, VCC, VCC); -- Node name is '|ramctrl16:231|:22' = '|ramctrl16:231|Phase3' -- Equation name is '_LC3_D3', type is buried _LC3_D3 = DFFE( _LC2_D3, GLOBAL( ExtClock0), VCC, VCC, VCC); -- Node name is '|ramctrl16:231|:39' = '|ramctrl16:231|Phase4' -- Equation name is '_LC2_F17', type is buried _LC2_F17 = DFFE( _LC3_D3, GLOBAL( ExtClock0), VCC, VCC, VCC); -- Node name is '|ramctrl16:231|:40' = '|ramctrl16:231|Phase5' -- Equation name is '_LC1_F17', type is buried _LC1_F17 = DFFE( _LC2_F17, GLOBAL( ExtClock0), VCC, VCC, VCC); -- Node name is '|ramctrl16:231|:53' = '|ramctrl16:231|RDEL' -- Equation name is '_LC6_F11', type is buried _LC6_F11 = DFFE( VCC, GLOBAL( ExtClock0), VCC, VCC, _LC3_F18); -- Node name is '|ramctrl16:231|:52' = '|ramctrl16:231|WREL' -- Equation name is '_LC8_F11', type is buried _LC8_F11 = DFFE( _EQ024, GLOBAL( ExtClock0), VCC, VCC, _LC3_F18); _EQ024 = !/IOW & !TA1; -- Node name is '|ramctrl16:231|:29' -- Equation name is '_LC1_F18', type is buried _LC1_F18 = DFFE( Enable, GLOBAL( ExtClock0), VCC, VCC, VCC); -- Node name is '|ramctrl16:231|:37' -- Equation name is '_LC3_A15', type is buried _LC3_A15 = LCELL( _EQ025); _EQ025 = _LC3_D3 # _LC3_F18; -- Node name is '|ramctrl16:231|:47' -- Equation name is '_LC3_F11', type is buried _LC3_F11 = LCELL( _EQ026); _EQ026 = _LC2_D3 & _LC6_F11; -- Node name is '|ramctrl16:231|:48' -- Equation name is '_LC7_F11', type is buried _LC7_F11 = LCELL( _EQ027); _EQ027 = _LC1_F17 & _LC6_F11; -- Node name is '/IORREQ' -- Equation name is '/IORREQ', type is output /IORREQ = VCC; -- Node name is ':246' -- Equation name is '_LC2_F11', type is buried _LC2_F11 = DFFE( _EQ028, GLOBAL( ExtClock0), VCC, VCC, VCC); _EQ028 = _LC5_F11 # !/IOW & !TA1; -- Node name is ':248' -- Equation name is '_LC4_F11', type is buried _LC4_F11 = LCELL( _EQ029); _EQ029 = !/IOW & TA1; -- Node name is ':253' -- Equation name is '_LC5_F11', type is buried _LC5_F11 = DFFE( _EQ030, GLOBAL( BCLK), VCC, VCC, VCC); _EQ030 = !/IOW & TA1; Project Information c:\max2work\kumagai\univ_if\uifbase\uif10k_ramrw.rpt ** COMPILATION SETTINGS & TIMES ** Processing Menu Commands ------------------------ Design Doctor = off Logic Synthesis: Synthesis Type Used = Multi-Level Default Synthesis Style = NORMAL Logic option settings in 'NORMAL' style for 'FLEX10KA' family CARRY_CHAIN = ignore CARRY_CHAIN_LENGTH = 32 CASCADE_CHAIN = ignore CASCADE_CHAIN_LENGTH = 2 DECOMPOSE_GATES = on DUPLICATE_LOGIC_EXTRACTION = on MINIMIZATION = full MULTI_LEVEL_FACTORING = on NOT_GATE_PUSH_BACK = on REDUCE_LOGIC = on REFACTORIZATION = on REGISTER_OPTIMIZATION = on RESYNTHESIZE_NETWORK = on SLOW_SLEW_RATE = off SUBFACTOR_EXTRACTION = on IGNORE_SOFT_BUFFERS = on USE_LPM_FOR_AHDL_OPERATORS = off Other logic synthesis settings: Automatic Global Clock = on Automatic Global Clear = on Automatic Global Preset = on Automatic Global Output Enable = on Automatic Fast I/O = off Automatic Register Packing = off Automatic Open-Drain Pins = on Automatic Implement in EAB = off Optimize = 5 Default Timing Specifications: None Cut All Bidir Feedback Timing Paths = on Cut All Clear & Preset Timing Paths = on Ignore Timing Assignments = on Functional SNF Extractor = off Linked SNF Extractor = off Timing SNF Extractor = on Optimize Timing SNF = off Generate AHDL TDO File = off Fitter Settings = NORMAL Use Quartus Fitter = on Smart Recompile = off Total Recompile = off Interfaces Menu Commands ------------------------ EDIF Netlist Writer = off Verilog Netlist Writer = off VHDL Netlist Writer = off Compilation Times ----------------- Compiler Netlist Extractor 00:00:00 Database Builder 00:00:01 Logic Synthesizer 00:00:00 Partitioner 00:00:01 Fitter 00:00:08 Timing SNF Extractor 00:00:00 Assembler 00:00:04 -------------------------- -------- Total Time 00:00:14 Memory Allocated ----------------- Peak memory allocated during compilation = 22,840K