Project Information c:\max2work\kumagai\univ_if\uifbase\uif_ramrw_16m.rpt MAX+plus II Compiler Report File Version 10.1 06/12/2001 Compiled: 02/07/2003 18:14:18 Copyright (C) 1988-2001 Altera Corporation Any megafunction design, and related net list (encrypted or decrypted), support information, device programming or simulation file, and any other associated documentation or information provided by Altera or a partner under Altera's Megafunction Partnership Program may be used only to program PLD devices (but not masked PLD devices) from Altera. Any other use of such megafunction design, net list, support information, device programming or simulation file, or any other related documentation or information is prohibited for any other purpose, including, but not limited to modification, reverse engineering, de-compiling, or use with any other silicon devices, unless such use is explicitly licensed under a separate agreement with Altera or a megafunction partner. Title to the intellectual property, including patents, copyrights, trademarks, trade secrets, or maskworks, embodied in any such megafunction design, net list, support information, device programming or simulation file, or any other related documentation or information provided by Altera or a megafunction partner, remains with Altera, the megafunction partner, or their respective licensors. No other licenses, including any licenses needed under any third party's intellectual property, are provided herein. ***** Project compilation was successful ** DEVICE SUMMARY ** Chip/ Input Output Bidir LCs POF Device Pins Pins Pins LCs % Utilized uif_ramrw_16m EPF6024AQC208-3 42 20 65 99 5 % User Pins: 42 20 65 Project Information c:\max2work\kumagai\univ_if\uifbase\uif_ramrw_16m.rpt ** PROJECT COMPILATION MESSAGES ** Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:21|dout7' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:21|dout6' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:21|dout5' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:21|dout4' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:21|dout3' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:21|dout2' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:21|dout1' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:21|dout0' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:12|dout7' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:12|dout6' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:12|dout5' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:12|dout4' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:12|dout3' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:12|dout2' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:12|dout1' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:12|dout0' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:1|dout7' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:1|dout6' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:1|dout5' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:1|dout4' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:1|dout3' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:1|dout2' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:1|dout1' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:1|dout0' is permanently disabled Warning: TRI or OPNDRN buffer ':98' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:21|dout7' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:21|dout6' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:21|dout5' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:21|dout4' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:21|dout3' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:21|dout2' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:21|dout1' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:21|dout0' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:12|dout7' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:12|dout6' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:12|dout5' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:12|dout4' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:12|dout3' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:12|dout2' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:12|dout1' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:12|dout0' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:1|dout7' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:1|dout6' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:1|dout5' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:1|dout4' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:1|dout3' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:1|dout2' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:1|dout1' is permanently disabled Warning: TRI or OPNDRN buffer '|LPM_BUSTRI:1|dout0' is permanently disabled Warning: TRI or OPNDRN buffer ':98' is permanently disabled Info: Reserved unused input pin 'TA16' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board Info: Reserved unused input pin 'TA15' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board Info: Reserved unused input pin 'TA14' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board Info: Reserved unused input pin 'TA13' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board Info: Reserved unused input pin 'TA12' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board Info: Reserved unused input pin 'TA11' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board Info: Reserved unused input pin 'TA10' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board Info: Reserved unused input pin 'TA9' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board Info: Reserved unused input pin 'TA8' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board Info: Reserved unused input pin 'TA7' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board Info: Reserved unused input pin 'TA6' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board Info: Reserved unused input pin 'TA5' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board Info: Reserved unused input pin 'TA4' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board Info: Reserved unused input pin 'TA3' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board Info: Reserved unused input pin 'TA2' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board Info: Reserved unused input pin 'TA0' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board Info: Reserved unused input pin 'ExtClock1' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board Info: Reserved unused input pin '/TOUT' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board Info: Reserved unused input pin '/TRESET' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board Info: Reserved unused input pin '/IRC3' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board Info: Reserved unused input pin '/IRC2' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board Info: Reserved unused input pin '/IRC1' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board Info: Reserved unused input pin '/IRC0' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board Info: Reserved unused input pin '/IORACK' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board Info: Reserved unused input pin '/MEMCS' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board Info: Reserved unused input pin '/ROMCS' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board Info: Reserved unused input pin '/MRD' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board Info: Reserved unused input pin '/MWR' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board Info: Reserved unused input pin '/IOR' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board Info: Reserved unused input pin '/IOCS7' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board Info: Reserved unused input pin '/IOCS6' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board Info: Reserved unused input pin '/IOCS5' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board Info: Reserved unused input pin '/IOCS4' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board Info: Reserved unused input pin '/IOCS3' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board Info: Reserved unused input pin '/IOCS1' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board Info: Reserved unused input pin '/IOCS0' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board Info: Reserved unused input pin '/BHE' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board Project Information c:\max2work\kumagai\univ_if\uifbase\uif_ramrw_16m.rpt ** PIN/LOCATION/CHIP ASSIGNMENTS ** Actual User Assignments Assignments (if different) Node Name uif_ramrw_16m@28 BCLK uif_ramrw_16m@197 /BHE uif_ramrw_16m@128 ExtClock0 uif_ramrw_16m@132 ExtClock1 uif_ramrw_16m@127 ExtIO0 uif_ramrw_16m@133 ExtIO1 uif_ramrw_16m@145 IOA_DIR uif_ramrw_16m@146 IOA_EN uif_ramrw_16m@143 IOA0 uif_ramrw_16m@142 IOA1 uif_ramrw_16m@141 IOA2 uif_ramrw_16m@139 IOA3 uif_ramrw_16m@138 IOA4 uif_ramrw_16m@137 IOA5 uif_ramrw_16m@136 IOA6 uif_ramrw_16m@134 IOA7 uif_ramrw_16m@125 IOB_DIR uif_ramrw_16m@126 IOB_EN uif_ramrw_16m@123 IOB0 uif_ramrw_16m@122 IOB1 uif_ramrw_16m@121 IOB2 uif_ramrw_16m@120 IOB3 uif_ramrw_16m@119 IOB4 uif_ramrw_16m@118 IOB5 uif_ramrw_16m@117 IOB6 uif_ramrw_16m@116 IOB7 uif_ramrw_16m@108 IOC_DIR uif_ramrw_16m@109 IOC_EN uif_ramrw_16m@155 /IOCS0 uif_ramrw_16m@156 /IOCS1 uif_ramrw_16m@157 /IOCS2 uif_ramrw_16m@158 /IOCS3 uif_ramrw_16m@160 /IOCS4 uif_ramrw_16m@161 /IOCS5 uif_ramrw_16m@163 /IOCS6 uif_ramrw_16m@164 /IOCS7 uif_ramrw_16m@106 IOC0 uif_ramrw_16m@105 IOC1 uif_ramrw_16m@104 IOC2 uif_ramrw_16m@103 IOC3 uif_ramrw_16m@101 IOC4 uif_ramrw_16m@100 IOC5 uif_ramrw_16m@99 IOC6 uif_ramrw_16m@98 IOC7 uif_ramrw_16m@92 IOD_DIR uif_ramrw_16m@93 IOD_EN uif_ramrw_16m@90 IOD0 uif_ramrw_16m@89 IOD1 uif_ramrw_16m@88 IOD2 uif_ramrw_16m@87 IOD3 uif_ramrw_16m@86 IOD4 uif_ramrw_16m@85 IOD5 uif_ramrw_16m@84 IOD6 uif_ramrw_16m@83 IOD7 uif_ramrw_16m@72 IOE_DIR uif_ramrw_16m@73 IOE_EN uif_ramrw_16m@71 IOE0 uif_ramrw_16m@70 IOE1 uif_ramrw_16m@69 IOE2 uif_ramrw_16m@68 IOE3 uif_ramrw_16m@67 IOE4 uif_ramrw_16m@66 IOE5 uif_ramrw_16m@65 IOE6 uif_ramrw_16m@64 IOE7 uif_ramrw_16m@60 IOF_DIR uif_ramrw_16m@61 IOF_EN uif_ramrw_16m@59 IOF0 uif_ramrw_16m@58 IOF1 uif_ramrw_16m@57 IOF2 uif_ramrw_16m@56 IOF3 uif_ramrw_16m@55 IOF4 uif_ramrw_16m@54 IOF5 uif_ramrw_16m@53 IOF6 uif_ramrw_16m@52 IOF7 uif_ramrw_16m@29 /IOR uif_ramrw_16m@33 /IORACK uif_ramrw_16m@31 IORDY uif_ramrw_16m@32 /IORREQ uif_ramrw_16m@30 /IOW uif_ramrw_16m@39 /IRC0 uif_ramrw_16m@40 /IRC1 uif_ramrw_16m@41 /IRC2 uif_ramrw_16m@42 /IRC3 uif_ramrw_16m@34 IRQ0 uif_ramrw_16m@35 IRQ1 uif_ramrw_16m@36 IRQ2 uif_ramrw_16m@37 IRQ3 uif_ramrw_16m@20 /MEMCS uif_ramrw_16m@22 /MRD uif_ramrw_16m@23 /MWR uif_ramrw_16m@21 /ROMCS uif_ramrw_16m@196 TA0 uif_ramrw_16m@195 TA1 uif_ramrw_16m@194 TA2 uif_ramrw_16m@193 TA3 uif_ramrw_16m@192 TA4 uif_ramrw_16m@191 TA5 uif_ramrw_16m@190 TA6 uif_ramrw_16m@189 TA7 uif_ramrw_16m@188 TA8 uif_ramrw_16m@177 TA9 uif_ramrw_16m@176 TA10 uif_ramrw_16m@175 TA11 uif_ramrw_16m@173 TA12 uif_ramrw_16m@172 TA13 uif_ramrw_16m@171 TA14 uif_ramrw_16m@170 TA15 uif_ramrw_16m@168 TA16 uif_ramrw_16m@48 TCLK uif_ramrw_16m@203 TD0 uif_ramrw_16m@204 TD1 uif_ramrw_16m@205 TD2 uif_ramrw_16m@206 TD3 uif_ramrw_16m@207 TD4 uif_ramrw_16m@208 TD5 uif_ramrw_16m@1 TD6 uif_ramrw_16m@2 TD7 uif_ramrw_16m@3 TD8 uif_ramrw_16m@4 TD9 uif_ramrw_16m@11 TD10 uif_ramrw_16m@12 TD11 uif_ramrw_16m@13 TD12 uif_ramrw_16m@14 TD13 uif_ramrw_16m@15 TD14 uif_ramrw_16m@16 TD15 uif_ramrw_16m@49 /TOUT uif_ramrw_16m@24 /TRESET Project Information c:\max2work\kumagai\univ_if\uifbase\uif_ramrw_16m.rpt ** FILE HIERARCHY ** |lpm_bustri:21| |lpm_bustri:12| |lpm_bustri:1| |lpm_bustri:45| |uif_ramif:219| |uif_ramif:219|lpm_bustri:24| |uif_ramif:219|lpm_bustri:26| |ramctrl16:231| |ramctrl16:231|busmux:33| |ramctrl16:231|busmux:33|lpm_mux:52| |ramctrl16:231|busmux:33|lpm_mux:52|altshift:external_latency_ffs| |ramctrl16:231|busmux:33|lpm_mux:52|muxlut:77| |ramctrl16:231|busmux:33|lpm_mux:52|muxlut:92| |ramctrl16:231|busmux:33|lpm_mux:52|muxlut:107| |ramctrl16:231|busmux:33|lpm_mux:52|muxlut:122| |ramctrl16:231|busmux:33|lpm_mux:52|muxlut:137| |ramctrl16:231|busmux:33|lpm_mux:52|muxlut:152| |ramctrl16:231|busmux:33|lpm_mux:52|muxlut:167| |ramctrl16:231|busmux:33|lpm_mux:52|muxlut:182| |pllunit_66:257| |pllunit_66:257|lpm_counter:4| |pllunit_66:257|lpm_counter:4|lpm_constant:scdw| |pllunit_66:257|lpm_counter:9| |pllunit_66:257|lpm_counter:9|lpm_constant:scdw| |pllunit_66:257|lpm_counter:9|lpm_compare:75| |pllunit_66:257|lpm_counter:9|lpm_compare:75|comptree:comparator| |pllunit_66:257|lpm_counter:9|lpm_compare:75|comptree:comparator|cmpchain:cmp_end| |pllunit_66:257|lpm_counter:9|lpm_compare:75|comptree:comparator|cmpchain:cmp_end|comptree:comp| |pllunit_66:257|lpm_counter:9|lpm_compare:75|comptree:comparator|cmpchain:cmp_end|comptree:comp|cmpchain:cmp0| |pllunit_66:257|lpm_counter:9|lpm_compare:75|comptree:comparator|cmpchain:cmp_end|comptree:comp|cmpchain:cmp_end| |pllunit_66:257|lpm_counter:9|lpm_compare:75|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree| |pllunit_66:257|lpm_counter:9|lpm_compare:75|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|cmpchain:cmp_end| |pllunit_66:257|lpm_counter:9|lpm_compare:75|altshift:aeb_ext_lat_ffs| |pllunit_66:257|lpm_counter:9|lpm_compare:75|altshift:agb_ext_lat_ffs| |pllunit_66:257|lpm_counter:5| |pllunit_66:257|lpm_counter:5|lpm_constant:scdw| Device-Specific Information:c:\max2work\kumagai\univ_if\uifbase\uif_ramrw_16m.rpt uif_ramrw_16m ***** Logic for device 'uif_ramrw_16m' compiled without errors. Device: EPF6024AQC208-3 FLEX 6000 Configuration Scheme: Passive Serial Device Options: User-Supplied Start-Up Clock = OFF Auto-Restart Configuration on Frame Error = OFF Release Clears Before Tri-States = OFF Enable Chip_Wide Reset = OFF Enable Chip-Wide Output Enable = OFF Enable INIT_DONE Output = ON Enable JTAG Support = OFF MultiVolt I/O = OFF R R R R R R R R R R R R R R E E E E E E E E E E E E E E S S S S S S ^ S S S S S S / / S / / S / / E E V E E E E ^ V D E E E E E E V I I E I I E I I R R C R / R R R D C A R R R T T R T T T T R T R C O O R O O R O O T T T T T T V V C G V B T T T T T T T T T V V V C C G T V V V T A A V A A A A V A V C G C C V C C V C C D D D D D D E E I N E H A A A A A A A A A E E E L I N A E E E A 1 1 E 1 1 1 1 E 1 E I N S S E S S E S S 5 4 3 2 1 0 D D O D D E 0 1 2 3 4 5 6 7 8 D D D K O D 0 D D D 9 0 1 D 2 3 4 5 D 6 D O D 7 6 D 5 4 D 3 2 ----------------------------------------------------------------------------------------------------------_ / 208 206 204 202 200 198 196 194 192 190 188 186 184 182 180 178 176 174 172 170 168 166 164 162 160 158 |_ / 207 205 203 201 199 197 195 193 191 189 187 185 183 181 179 177 175 173 171 169 167 165 163 161 159 157 | TD6 | 1 156 | /IOCS1 TD7 | 2 155 | /IOCS0 TD8 | 3 154 | RESERVED TD9 | 4 153 | RESERVED RESERVED | 5 152 | RESERVED ^nCE | 6 151 | RESERVED GND | 7 150 | ^CONF_DONE VCCINT | 8 149 | VCCIO VCCIO | 9 148 | VCCINT RESERVED | 10 147 | GND TD10 | 11 146 | IOA_EN TD11 | 12 145 | IOA_DIR TD12 | 13 144 | RESERVED TD13 | 14 143 | IOA0 TD14 | 15 142 | IOA1 TD15 | 16 141 | IOA2 RESERVED | 17 140 | RESERVED RESERVED | 18 139 | IOA3 RESERVED | 19 138 | IOA4 /MEMCS | 20 137 | IOA5 /ROMCS | 21 136 | IOA6 /MRD | 22 135 | @INIT_DONE /MWR | 23 134 | IOA7 /TRESET | 24 133 | ExtIO1 GND | 25 132 | ExtClock1 VCCINT | 26 131 | VCCIO VCCIO | 27 EPF6024AQC208-3 130 | VCCINT BCLK | 28 129 | GND /IOR | 29 128 | ExtClock0 /IOW | 30 127 | ExtIO0 IORDY | 31 126 | IOB_EN /IORREQ | 32 125 | IOB_DIR /IORACK | 33 124 | RESERVED IRQ0 | 34 123 | IOB0 IRQ1 | 35 122 | IOB1 IRQ2 | 36 121 | IOB2 IRQ3 | 37 120 | IOB3 RESERVED | 38 119 | IOB4 /IRC0 | 39 118 | IOB5 /IRC1 | 40 117 | IOB6 /IRC2 | 41 116 | IOB7 /IRC3 | 42 115 | RESERVED GND | 43 114 | RESERVED VCCINT | 44 113 | RESERVED VCCIO | 45 112 | VCCIO ^MSEL | 46 111 | VCCINT RESERVED | 47 110 | GND TCLK | 48 109 | IOC_EN /TOUT | 49 108 | IOC_DIR RESERVED | 50 107 | RESERVED RESERVED | 51 106 | IOC0 IOF7 | 52 105 | IOC1 | 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 _| \ 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 | \----------------------------------------------------------------------------------------------------------- I I I I I I I I I G V I I I I I I I I I I R R R ^ G V ^ R R I I I I I I I I R I I R G V R I I I I R I I O O O O O O O O O N C O O O O O O O O O O E E E n N C n E E O O O O O O O O E O O E N C E O O O O E O O F F F F F F F F F D C E E E E E E E E E E S S S C D C S S S D D D D D D D D S D D S D C S C C C C S C C 6 5 4 3 2 1 0 _ _ I 7 6 5 4 3 2 1 0 _ _ E E E O I T E E 7 6 5 4 3 2 1 0 E _ _ E I E 7 6 5 4 E 3 2 D E O D E R R R N O A R R R D E R O R R I N I N V V V F T V V V I N V V V R R E E E I U E E E R E E E D D D G S D D D D D D N.C. = No Connect. This pin has no internal connection to the device. VCCINT = Dedicated power pin, which MUST be connected to VCC (3.3 volts). VCCIO = Dedicated power pin, which MUST be connected to VCC (3.3 volts). GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND. RESERVED = Unused I/O pin, which MUST be left unconnected. ^ = Dedicated configuration pin. + = Reserved configuration pin, which is tri-stated during user mode. * = Reserved configuration pin, which drives out in user mode. PDn = Power Down pin. @ = Special-purpose pin. # = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use. & = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions. Device-Specific Information:c:\max2work\kumagai\univ_if\uifbase\uif_ramrw_16m.rpt uif_ramrw_16m ** RESOURCE USAGE ** Logic Column Row Array Interconnect Interconnect Sync. Sync. Left External Right External Borrowed LC1 Block Logic Cells Driven Driven Clocks Clears Clear Load Interconnect Interconnect Inputs A1 9/10( 90%) 9/10( 90%) 0/10( 0%) 1/2 0/2 0/1 0/1 2/22( 9%) 9/22( 40%) 0/4 A3 5/10( 50%) 5/10( 50%) 0/10( 0%) 1/2 0/2 0/1 0/1 4/22( 18%) 4/22( 18%) 0/4 A15 1/10( 10%) 1/10( 10%) 0/10( 0%) 0/2 0/2 0/1 0/1 0/22( 0%) 1/22( 4%) 0/4 B1 4/10( 40%) 4/10( 40%) 0/10( 0%) 1/2 0/2 0/1 0/1 1/22( 4%) 5/22( 22%) 0/4 B22 3/10( 30%) 1/10( 10%) 0/10( 0%) 1/2 0/2 0/1 0/1 1/22( 4%) 1/22( 4%) 0/4 B24 7/10( 70%) 0/10( 0%) 0/10( 0%) 1/2 0/2 1/1 0/1 1/22( 4%) 0/22( 0%) 1/4 C1 7/10( 70%) 6/10( 60%) 0/10( 0%) 1/2 0/2 0/1 0/1 2/22( 9%) 8/22( 36%) 0/4 D1 6/10( 60%) 2/10( 20%) 0/10( 0%) 1/2 0/2 0/1 0/1 2/22( 9%) 2/22( 9%) 0/4 D4 5/10( 50%) 4/10( 40%) 0/10( 0%) 1/2 0/2 0/1 0/1 3/22( 13%) 4/22( 18%) 0/4 D28 5/10( 50%) 0/10( 0%) 0/10( 0%) 1/2 0/2 0/1 0/1 0/22( 0%) 1/22( 4%) 0/4 G1 10/10(100%) 0/10( 0%) 0/10( 0%) 1/2 0/2 0/1 0/1 6/22( 27%) 6/22( 27%) 0/4 G2 2/10( 20%) 0/10( 0%) 0/10( 0%) 1/2 0/2 0/1 0/1 2/22( 9%) 2/22( 9%) 0/4 G3 1/10( 10%) 0/10( 0%) 0/10( 0%) 1/2 0/2 0/1 0/1 2/22( 9%) 0/22( 0%) 0/4 G4 2/10( 20%) 0/10( 0%) 0/10( 0%) 1/2 0/2 0/1 0/1 4/22( 18%) 1/22( 4%) 0/4 G5 2/10( 20%) 0/10( 0%) 0/10( 0%) 1/2 0/2 0/1 0/1 2/22( 9%) 2/22( 9%) 0/4 G6 2/10( 20%) 0/10( 0%) 0/10( 0%) 1/2 0/2 0/1 0/1 3/22( 13%) 1/22( 4%) 0/4 G7 1/10( 10%) 0/10( 0%) 0/10( 0%) 1/2 0/2 0/1 0/1 1/22( 4%) 1/22( 4%) 0/4 G8 2/10( 20%) 0/10( 0%) 0/10( 0%) 1/2 0/2 0/1 0/1 3/22( 13%) 1/22( 4%) 0/4 G9 9/10( 90%) 0/10( 0%) 0/10( 0%) 1/2 0/2 0/1 0/1 8/22( 36%) 5/22( 22%) 0/4 G10 4/10( 40%) 1/10( 10%) 0/10( 0%) 1/2 0/2 0/1 0/1 4/22( 18%) 3/22( 13%) 0/4 G11 3/10( 30%) 0/10( 0%) 0/10( 0%) 1/2 0/2 0/1 0/1 2/22( 9%) 3/22( 13%) 0/4 G13 1/10( 10%) 0/10( 0%) 0/10( 0%) 1/2 0/2 0/1 0/1 1/22( 4%) 2/22( 9%) 0/4 G16 1/10( 10%) 1/10( 10%) 0/10( 0%) 1/2 0/2 0/1 0/1 1/22( 4%) 2/22( 9%) 0/4 G17 1/10( 10%) 0/10( 0%) 0/10( 0%) 1/2 0/2 0/1 0/1 1/22( 4%) 1/22( 4%) 0/4 G18 2/10( 20%) 2/10( 20%) 0/10( 0%) 1/2 0/2 0/1 0/1 2/22( 9%) 2/22( 9%) 0/4 G19 1/10( 10%) 1/10( 10%) 0/10( 0%) 1/2 0/2 0/1 0/1 1/22( 4%) 2/22( 9%) 0/4 G20 2/10( 20%) 2/10( 20%) 0/10( 0%) 1/2 0/2 0/1 0/1 2/22( 9%) 2/22( 9%) 0/4 G21 1/10( 10%) 1/10( 10%) 0/10( 0%) 1/2 0/2 0/1 0/1 1/22( 4%) 2/22( 9%) 0/4 Total dedicated input pins used: 4/4 (100%) Total I/O pins used: 124/167 ( 74%) Total logic cells used: 99/1960 ( 5%) Average fan-in: 3.13/4 ( 78%) Total fan-in: 310/7840 ( 3%) Total input pins required: 42 Total output pins required: 20 Total bidirectional pins required: 65 Total reserved pins required 1 Total logic cells required: 99 Total flipflops required: 84 Total packed registers required: 0 Total logic cells in carry chains: 9 Total number of carry chains: 2 Total number of carry chains of length 1-9 : 2 Total logic cells in cascade chains: 2 Total number of cascade chains: 1 Logic cells inserted for fitting: 1 Synthesized logic cells: 11/1960 ( 0%) Logic Cell Counts Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Total A: 9 0 5 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 15 B: 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0 7 0 0 0 0 14 C: 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 D: 6 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 16 E: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 G: 10 2 1 2 2 2 1 2 9 4 3 0 1 0 0 1 1 2 1 2 1 0 0 0 0 0 0 0 47 Total: 36 2 6 7 2 2 1 2 9 4 3 0 1 0 1 1 1 2 1 2 1 3 0 7 0 0 0 5 99 Device-Specific Information:c:\max2work\kumagai\univ_if\uifbase\uif_ramrw_16m.rpt uif_ramrw_16m ** INPUTS ** Fan-In Fan-Out Pin LC Row Col Primitive Code INP FBK OUT FBK Name 28 - - -- INPUT G 0 0 0 0 BCLK 197 - - 06 INPUT 0 0 0 0 /BHE 128 - - -- INPUT G 0 0 0 0 ExtClock0 132 - - -- INPUT 0 0 0 0 ExtClock1 143 - B -- BIDIR 0 0 0 0 IOA0 142 - C -- BIDIR 0 0 0 0 IOA1 141 - C -- BIDIR 0 0 0 0 IOA2 139 - C -- BIDIR 0 0 0 0 IOA3 138 - C -- BIDIR 0 0 0 0 IOA4 137 - C -- BIDIR 0 0 0 0 IOA5 136 - C -- BIDIR 0 0 0 0 IOA6 134 - D -- BIDIR 0 0 0 0 IOA7 123 - E -- BIDIR 0 0 0 0 IOB0 122 - E -- BIDIR 0 0 0 0 IOB1 121 - E -- BIDIR 0 0 0 0 IOB2 120 - E -- BIDIR 0 0 0 0 IOB3 119 - E -- BIDIR 0 0 0 0 IOB4 118 - E -- BIDIR 0 0 0 0 IOB5 117 - E -- BIDIR 0 0 0 0 IOB6 116 - F -- BIDIR 0 0 0 0 IOB7 155 - A -- INPUT 0 0 0 0 /IOCS0 156 - A -- INPUT 0 0 0 0 /IOCS1 157 - A -- INPUT 0 0 0 1 /IOCS2 158 - A -- INPUT 0 0 0 0 /IOCS3 160 - - 28 INPUT 0 0 0 0 /IOCS4 161 - - 27 INPUT 0 0 0 0 /IOCS5 163 - - 26 INPUT 0 0 0 0 /IOCS6 164 - - 25 INPUT 0 0 0 0 /IOCS7 106 - G -- BIDIR 0 0 0 0 IOC0 105 - G -- BIDIR 0 0 0 0 IOC1 104 - G -- BIDIR 0 0 0 0 IOC2 103 - G -- BIDIR 0 0 0 0 IOC3 101 - G -- BIDIR 0 0 0 0 IOC4 100 - - 28 BIDIR 0 0 0 0 IOC5 99 - - 27 BIDIR 0 0 0 0 IOC6 98 - - 26 BIDIR 0 0 0 0 IOC7 90 - - 21 BIDIR 0 1 0 2 IOD0 89 - - 20 BIDIR 0 1 0 2 IOD1 88 - - 20 BIDIR 0 1 0 2 IOD2 87 - - 19 BIDIR 0 1 0 2 IOD3 86 - - 18 BIDIR 0 1 0 2 IOD4 85 - - 17 BIDIR 0 1 0 2 IOD5 84 - - 17 BIDIR 0 1 0 0 IOD6 83 - - 16 BIDIR 0 1 0 2 IOD7 71 - - 10 BIDIR 0 1 0 0 IOE0 70 - - 10 BIDIR 0 1 0 2 IOE1 69 - - 09 BIDIR 0 1 0 0 IOE2 68 - - 08 BIDIR 0 1 0 0 IOE3 67 - - 07 BIDIR 0 1 0 0 IOE4 66 - - 07 BIDIR 0 1 0 0 IOE5 65 - - 06 BIDIR 0 1 0 0 IOE6 64 - - 05 BIDIR 0 1 0 0 IOE7 59 - - 03 BIDIR 0 1 0 0 IOF0 58 - - 03 BIDIR 0 1 0 0 IOF1 57 - - 02 BIDIR 0 1 0 0 IOF2 56 - - 01 BIDIR 0 1 0 0 IOF3 55 - G -- BIDIR 0 1 0 0 IOF4 54 - G -- BIDIR 0 1 0 0 IOF5 53 - G -- BIDIR 0 1 0 0 IOF6 52 - G -- BIDIR 0 1 0 0 IOF7 29 - D -- INPUT 0 0 0 0 /IOR 33 - E -- INPUT 0 0 0 0 /IORACK 30 - D -- INPUT 0 0 0 19 /IOW 39 - F -- INPUT 0 0 0 0 /IRC0 40 - F -- INPUT 0 0 0 0 /IRC1 41 - F -- INPUT 0 0 0 0 /IRC2 42 - F -- INPUT 0 0 0 0 /IRC3 20 - D -- INPUT 0 0 0 0 /MEMCS 22 - D -- INPUT 0 0 0 0 /MRD 23 - D -- INPUT 0 0 0 0 /MWR 21 - D -- INPUT 0 0 0 0 /ROMCS 196 - - 06 INPUT 0 0 0 0 TA0 195 - - 07 INPUT 0 0 0 19 TA1 194 - - 08 INPUT 0 0 0 0 TA2 193 - - 08 INPUT 0 0 0 0 TA3 192 - - 09 INPUT 0 0 0 0 TA4 191 - - 10 INPUT 0 0 0 0 TA5 190 - - 11 INPUT 0 0 0 0 TA6 189 - - 11 INPUT 0 0 0 0 TA7 188 - - 12 INPUT 0 0 0 0 TA8 177 - - 18 INPUT 0 0 0 0 TA9 176 - - 18 INPUT 0 0 0 0 TA10 175 - - 19 INPUT 0 0 0 0 TA11 173 - - 21 INPUT 0 0 0 0 TA12 172 - - 21 INPUT 0 0 0 0 TA13 171 - - 22 INPUT 0 0 0 0 TA14 170 - - 22 INPUT 0 0 0 0 TA15 168 - - 23 INPUT 0 0 0 0 TA16 48 - F -- BIDIR 0 0 0 0 TCLK 203 - - 02 BIDIR 0 1 0 2 TD0 204 - - 01 BIDIR 0 1 0 2 TD1 205 - A -- BIDIR 0 1 0 2 TD2 206 - A -- BIDIR 0 1 0 2 TD3 207 - A -- BIDIR 0 1 0 2 TD4 208 - A -- BIDIR 0 1 0 2 TD5 1 - A -- BIDIR 0 1 0 2 TD6 2 - A -- BIDIR 0 1 0 2 TD7 3 - A -- BIDIR 0 1 0 2 TD8 4 - B -- BIDIR 0 1 0 2 TD9 11 - B -- BIDIR 0 1 0 2 TD10 12 - B -- BIDIR 0 1 0 2 TD11 13 - B -- BIDIR 0 1 0 2 TD12 14 - C -- BIDIR 0 1 0 2 TD13 15 - C -- BIDIR 0 1 0 2 TD14 16 - C -- BIDIR 0 1 0 1 TD15 49 - F -- INPUT 0 0 0 0 /TOUT 24 - - -- INPUT 0 0 0 0 /TRESET Code: s = Synthesized pin or logic cell + = Synchronous flipflop / = Slow slew-rate output ! = NOT gate push-back r = Fitter-inserted logic cell ^ = Increased input delay $ = Driven by fast output logic cell G = Global Source. Fan-out destinations counted here do not include destinations that are driven using global routing resources. Refer to the Auto Global Signals, Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals Sections of this Report File for information on which signals' fan-outs are used as Clock, Clear, Preset, Output Enable, and synchronous Load signals. Device-Specific Information:c:\max2work\kumagai\univ_if\uifbase\uif_ramrw_16m.rpt uif_ramrw_16m ** OUTPUTS ** Fed By Fan-In Fan-Out Pin LC Row Col Primitive Code INP FBK OUT FBK Name 127 - D -- OUTPUT $ 0 1 0 0 ExtIO0 133 - D -- OUTPUT 0 0 0 0 ExtIO1 145 - B -- OUTPUT 0 0 0 0 IOA_DIR 146 - B -- OUTPUT 0 0 0 0 IOA_EN 143 - B -- TRI 0 0 0 0 IOA0 142 - C -- TRI 0 0 0 0 IOA1 141 - C -- TRI 0 0 0 0 IOA2 139 - C -- TRI 0 0 0 0 IOA3 138 - C -- TRI 0 0 0 0 IOA4 137 - C -- TRI 0 0 0 0 IOA5 136 - C -- TRI 0 0 0 0 IOA6 134 - D -- TRI 0 0 0 0 IOA7 125 - D -- OUTPUT 0 0 0 0 IOB_DIR 126 - D -- OUTPUT 0 0 0 0 IOB_EN 123 - E -- TRI 0 0 0 0 IOB0 122 - E -- TRI 0 0 0 0 IOB1 121 - E -- TRI 0 0 0 0 IOB2 120 - E -- TRI 0 0 0 0 IOB3 119 - E -- TRI 0 0 0 0 IOB4 118 - E -- TRI 0 0 0 0 IOB5 117 - E -- TRI 0 0 0 0 IOB6 116 - F -- TRI 0 0 0 0 IOB7 108 - F -- OUTPUT 0 0 0 0 IOC_DIR 109 - F -- OUTPUT 0 0 0 0 IOC_EN 106 - G -- TRI 0 0 0 0 IOC0 105 - G -- TRI 0 0 0 0 IOC1 104 - G -- TRI 0 0 0 0 IOC2 103 - G -- TRI 0 0 0 0 IOC3 101 - G -- TRI 0 0 0 0 IOC4 100 - - 28 TRI 0 0 0 0 IOC5 99 - - 27 TRI 0 0 0 0 IOC6 98 - - 26 TRI 0 0 0 0 IOC7 92 - - 23 OUTPUT 0 0 0 0 IOD_DIR 93 - - 24 OUTPUT 0 0 0 0 IOD_EN 90 - - 21 TRI $ 0 1 0 2 IOD0 89 - - 20 TRI $ 0 1 0 2 IOD1 88 - - 20 TRI $ 0 1 0 2 IOD2 87 - - 19 TRI $ 0 1 0 2 IOD3 86 - - 18 TRI $ 0 1 0 2 IOD4 85 - - 17 TRI $ 0 1 0 2 IOD5 84 - - 17 TRI $ 0 1 0 0 IOD6 83 - - 16 TRI $ 0 1 0 2 IOD7 72 - - 11 OUTPUT 0 0 0 0 IOE_DIR 73 - - 12 OUTPUT 0 0 0 0 IOE_EN 71 - - 10 TRI $ 0 1 0 0 IOE0 70 - - 10 TRI $ 0 1 0 2 IOE1 69 - - 09 TRI $ 0 1 0 0 IOE2 68 - - 08 TRI $ 0 1 0 0 IOE3 67 - - 07 TRI $ 0 1 0 0 IOE4 66 - - 07 TRI $ 0 1 0 0 IOE5 65 - - 06 TRI $ 0 1 0 0 IOE6 64 - - 05 TRI $ 0 1 0 0 IOE7 60 - - 04 OUTPUT $ 0 1 0 0 IOF_DIR 61 - - 04 OUTPUT 0 0 0 0 IOF_EN 59 - - 03 TRI $ 0 1 0 0 IOF0 58 - - 03 TRI $ 0 1 0 0 IOF1 57 - - 02 TRI $ 0 1 0 0 IOF2 56 - - 01 TRI $ 0 1 0 0 IOF3 55 - G -- TRI $ 0 1 0 0 IOF4 54 - G -- TRI $ 0 1 0 0 IOF5 53 - G -- TRI $ 0 1 0 0 IOF6 52 - G -- TRI $ 0 1 0 0 IOF7 31 - D -- OUTPUT 0 0 0 0 IORDY 32 - E -- OUTPUT 0 0 0 0 /IORREQ 34 - E -- OUTPUT 0 0 0 0 IRQ0 35 - E -- OUTPUT 0 0 0 0 IRQ1 36 - E -- OUTPUT 0 0 0 0 IRQ2 37 - E -- OUTPUT 0 0 0 0 IRQ3 48 - F -- TRI 0 0 0 0 TCLK 203 - - 02 TRI $ 0 1 0 2 TD0 204 - - 01 TRI $ 0 1 0 2 TD1 205 - A -- TRI $ 0 1 0 2 TD2 206 - A -- TRI $ 0 1 0 2 TD3 207 - A -- TRI $ 0 1 0 2 TD4 208 - A -- TRI $ 0 1 0 2 TD5 1 - A -- TRI $ 0 1 0 2 TD6 2 - A -- TRI $ 0 1 0 2 TD7 3 - A -- TRI $ 0 1 0 2 TD8 4 - B -- TRI $ 0 1 0 2 TD9 11 - B -- TRI $ 0 1 0 2 TD10 12 - B -- TRI $ 0 1 0 2 TD11 13 - B -- TRI $ 0 1 0 2 TD12 14 - C -- TRI $ 0 1 0 2 TD13 15 - C -- TRI $ 0 1 0 2 TD14 16 - C -- TRI $ 0 1 0 1 TD15 Code: s = Synthesized pin or logic cell + = Synchronous flipflop / = Slow slew-rate output ! = NOT gate push-back r = Fitter-inserted logic cell ^ = Increased input delay $ = Driven by fast output logic cell Device-Specific Information:c:\max2work\kumagai\univ_if\uifbase\uif_ramrw_16m.rpt uif_ramrw_16m ** BURIED LOGIC ** Fan-In Fan-Out IOC LC Row Col Primitive Code INP FBK OUT FBK Name - 2 A 15 SOFT s r 1 0 0 0 /IOCS2~fit~out - 2 D 28 DFF + 0 0 0 0 |pllunit_66:257|C0 (|pllunit_66:257|LPM_COUNTER:4|dffs0) - 3 D 28 DFF + 0 1 0 1 |pllunit_66:257|C1 (|pllunit_66:257|LPM_COUNTER:4|dffs1) - 4 D 28 DFF + 0 1 0 1 |pllunit_66:257|C2 (|pllunit_66:257|LPM_COUNTER:4|dffs2) - 5 D 28 DFF + 0 1 0 2 |pllunit_66:257|C3 (|pllunit_66:257|LPM_COUNTER:4|dffs3) - 6 B 22 DFF + 0 2 0 2 |pllunit_66:257|V0 (|pllunit_66:257|LPM_COUNTER:5|dffs0) - 1 B 22 DFF + 0 4 0 2 |pllunit_66:257|V1 (|pllunit_66:257|LPM_COUNTER:5|dffs1) - 2 B 24 DFF + 0 1 0 1 |pllunit_66:257|LPM_COUNTER:9|q0 (|pllunit_66:257|LPM_COUNTER:9|dffs0) - 3 B 24 DFF + 0 2 0 2 |pllunit_66:257|LPM_COUNTER:9|q1 (|pllunit_66:257|LPM_COUNTER:9|dffs1) - 4 B 24 DFF + 0 2 0 2 |pllunit_66:257|LPM_COUNTER:9|q2 (|pllunit_66:257|LPM_COUNTER:9|dffs2) - 5 B 24 DFF + 0 2 0 4 |pllunit_66:257|LPM_COUNTER:9|q3 (|pllunit_66:257|LPM_COUNTER:9|dffs3) - 6 B 24 DFF + 0 2 0 2 |pllunit_66:257|LPM_COUNTER:9|q4 (|pllunit_66:257|LPM_COUNTER:9|dffs4) - 8 B 24 OR2 s ! 0 4 0 3 |pllunit_66:257|LPM_COUNTER:9|lpm_compare:75|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|cmpchain:cmp_end|~40~1 - 7 B 22 OR2 ! 0 2 0 1 |pllunit_66:257|LPM_COUNTER:9|lpm_compare:75|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|cmpchain:cmp_end|:40 - 7 B 24 LCELL 0 2 0 5 |pllunit_66:257|LPM_COUNTER:9|nClr - 1 D 28 OR2 0 2 1 0 |pllunit_66:257.DiffOut (|pllunit_66:257|:6) - 1 G 05 DFF + 0 3 1 1 |ramctrl16:231.MA1 (|ramctrl16:231|~11~1) - 1 G 03 DFF + 0 3 1 1 |ramctrl16:231.MA2 (|ramctrl16:231|~11~2) - 1 G 01 DFF + 0 3 1 1 |ramctrl16:231.MA3 (|ramctrl16:231|~11~3) - 4 G 01 DFF + 0 3 1 1 |ramctrl16:231.MA4 (|ramctrl16:231|~11~4) - 2 G 01 DFF + 0 3 1 1 |ramctrl16:231.MA5 (|ramctrl16:231|~11~5) - 3 G 01 DFF + 0 3 1 1 |ramctrl16:231.MA6 (|ramctrl16:231|~11~6) - 5 G 01 DFF + 0 3 1 1 |ramctrl16:231.MA7 (|ramctrl16:231|~11~7) - 1 G 02 DFF + 0 3 1 1 |ramctrl16:231.MA8 (|ramctrl16:231|~11~8) - 6 G 06 DFF + 0 3 1 1 |ramctrl16:231.MA9 (|ramctrl16:231|~11~9) - 6 G 07 DFF + 0 3 1 1 |ramctrl16:231.MA10 (|ramctrl16:231|~11~10) - 6 G 08 DFF + 0 3 1 1 |ramctrl16:231.MA11 (|ramctrl16:231|~11~11) - 6 G 09 DFF + 0 3 1 1 |ramctrl16:231.MA12 (|ramctrl16:231|~11~12) - 6 G 11 DFF + 0 3 1 1 |ramctrl16:231.MA13 (|ramctrl16:231|~11~13) - 6 G 17 DFF + 0 3 1 1 |ramctrl16:231.MA14 (|ramctrl16:231|~11~14) - 6 G 01 DFF + 0 3 1 1 |ramctrl16:231.MA15 (|ramctrl16:231|~11~15) - 6 D 01 DFF + 0 1 0 2 |ramctrl16:231|Phase1 (|ramctrl16:231|:12) - 2 G 10 DFF + 0 3 0 2 |ramctrl16:231|D8 (|ramctrl16:231|~18~1) - 7 D 04 DFF + 0 3 0 2 |ramctrl16:231|D9 (|ramctrl16:231|~18~2) - 9 G 09 DFF + 0 3 0 2 |ramctrl16:231|D10 (|ramctrl16:231|~18~3) - 2 G 09 DFF + 0 3 0 2 |ramctrl16:231|D11 (|ramctrl16:231|~18~4) - 8 G 09 DFF + 0 3 0 2 |ramctrl16:231|D12 (|ramctrl16:231|~18~5) - 5 C 01 DFF + 0 3 0 2 |ramctrl16:231|D13 (|ramctrl16:231|~18~6) - 6 C 01 DFF + 0 3 0 2 |ramctrl16:231|D14 (|ramctrl16:231|~18~7) - 7 C 01 DFF + 0 3 0 2 |ramctrl16:231|D15 (|ramctrl16:231|~18~8) - 6 A 03 DFF + 0 4 1 1 DR0 (|ramctrl16:231|~19~1) - 1 A 01 DFF + 0 4 1 1 DR1 (|ramctrl16:231|~19~2) - 7 A 01 DFF + 0 4 1 1 DR2 (|ramctrl16:231|~19~3) - 8 A 01 DFF + 0 4 1 1 DR3 (|ramctrl16:231|~19~4) - 9 A 01 DFF + 0 4 1 1 DR4 (|ramctrl16:231|~19~5) - 5 A 01 DFF + 0 4 1 1 DR5 (|ramctrl16:231|~19~6) - 6 A 01 DFF + 0 4 1 1 DR6 (|ramctrl16:231|~19~7) - 4 A 01 DFF + 0 4 1 1 DR7 (|ramctrl16:231|~19~8) - 4 D 01 AND2 s 0 3 0 1 |ramctrl16:231|Phase0~1 (|ramctrl16:231|~20~1) - 5 D 01 OR2 2 3 0 42 |ramctrl16:231|Phase0 (|ramctrl16:231|:20) - 1 D 01 DFF + 0 1 0 10 |ramctrl16:231|Phase2 (|ramctrl16:231|:21) - 2 A 03 DFF + 0 1 0 19 |ramctrl16:231|Phase3 (|ramctrl16:231|:22) - 6 G 04 DFF + 0 3 1 0 |ramctrl16:231.DWE (|ramctrl16:231|:24) - 2 D 01 DFF + 2 1 0 1 |ramctrl16:231|:29 - 2 A 01 DFF + 0 4 1 1 DR8 (|ramctrl16:231|~32~1) - 4 B 01 DFF + 0 4 1 1 DR9 (|ramctrl16:231|~32~2) - 3 B 01 DFF + 0 4 1 1 DR10 (|ramctrl16:231|~32~3) - 2 B 01 DFF + 0 4 1 1 DR11 (|ramctrl16:231|~32~4) - 1 B 01 DFF + 0 4 1 1 DR12 (|ramctrl16:231|~32~5) - 4 C 01 DFF + 0 4 1 1 DR13 (|ramctrl16:231|~32~6) - 2 C 01 DFF + 0 4 1 1 DR14 (|ramctrl16:231|~32~7) - 1 C 01 DFF + 0 4 1 1 DR15 (|ramctrl16:231|~32~8) - 1 G 10 OR2 s 0 4 0 1 |ramctrl16~231.MDW0~1 (|ramctrl16:231|~36~1~1) - 1 G 18 DFF + 0 4 1 1 |ramctrl16:231.MDW0 (|ramctrl16:231|~36~1) - 3 D 04 OR2 s 0 4 0 1 |ramctrl16~231.MDW1~1 (|ramctrl16:231|~36~2~1) - 6 G 20 DFF + 0 4 1 1 |ramctrl16:231.MDW1 (|ramctrl16:231|~36~2) - 3 G 09 OR2 s 0 4 0 1 |ramctrl16~231.MDW2~1 (|ramctrl16:231|~36~3~1) - 6 G 21 DFF + 0 4 1 1 |ramctrl16:231.MDW2 (|ramctrl16:231|~36~3) - 4 G 09 OR2 s 0 4 0 1 |ramctrl16~231.MDW3~1 (|ramctrl16:231|~36~4~1) - 1 G 20 DFF + 0 4 1 1 |ramctrl16:231.MDW3 (|ramctrl16:231|~36~4) - 5 G 09 OR2 s 0 4 0 1 |ramctrl16~231.MDW4~1 (|ramctrl16:231|~36~5~1) - 6 G 19 DFF + 0 4 1 1 |ramctrl16:231.MDW4 (|ramctrl16:231|~36~5) - 4 A 03 OR2 s 0 4 0 1 |ramctrl16~231.MDW5~1 (|ramctrl16:231|~36~6~1) - 6 G 18 DFF + 0 4 1 1 |ramctrl16:231.MDW5 (|ramctrl16:231|~36~6) - 7 A 03 OR2 s 0 4 0 1 |ramctrl16~231.MDW6~1 (|ramctrl16:231|~36~7~1) - 6 G 16 DFF + 0 4 1 1 |ramctrl16:231.MDW6 (|ramctrl16:231|~36~7) - 7 G 10 OR2 s 0 4 0 1 |ramctrl16~231.MDW7~1 (|ramctrl16:231|~36~8~1) - 6 G 10 DFF + 0 4 1 1 |ramctrl16:231.MDW7 (|ramctrl16:231|~36~8) - 3 A 03 DFF + 0 1 0 2 |ramctrl16:231|Phase4 (|ramctrl16:231|:39) - 3 A 01 DFF + 0 1 0 11 |ramctrl16:231|Phase5 (|ramctrl16:231|:40) - 7 G 09 DFF + 0 3 1 0 |ramctrl16:231.MA0 (|ramctrl16:231|:43) - 1 G 04 DFF + 2 2 0 2 |ramctrl16:231|WREL (|ramctrl16:231|:52) - 3 C 01 DFF + 0 2 0 17 |ramctrl16:231|RDEL (|ramctrl16:231|:53) - 6 G 05 DFF + 2 2 0 2 MA0 (~250~1) - 1 D 04 DFF + 2 2 0 2 MA1 (~250~2) - 7 G 13 DFF + 2 2 0 2 MA2 (~250~3) - 10 G 01 DFF + 2 2 0 2 MA3 (~250~4) - 8 G 01 DFF + 2 2 0 2 MA4 (~250~5) - 7 G 01 DFF + 2 2 0 2 MA5 (~250~6) - 2 G 11 DFF + 2 2 0 2 MA6 (~250~7) - 6 G 02 DFF + 2 2 0 2 MA7 (~250~8) - 1 G 06 DFF + 2 2 0 2 MA8 (~250~9) - 6 D 04 DFF + 2 2 0 2 MA9 (~250~10) - 1 G 08 DFF + 2 2 0 2 MA10 (~250~11) - 1 G 09 DFF + 2 2 0 2 MA11 (~250~12) - 7 G 11 DFF + 2 2 0 2 MA12 (~250~13) - 2 D 04 DFF + 2 2 0 2 MA13 (~250~14) - 9 G 01 DFF + 2 2 0 2 MA14 (~250~15) - 3 D 01 DFF + 2 0 0 2 :253 - 2 D 28 CARRY 0 0 0 1 |pllunit_66:257|LPM_COUNTER:4|carrybit1 - 3 D 28 CARRY 0 2 0 1 |pllunit_66:257|LPM_COUNTER:4|carrybit2 - 4 D 28 CARRY 0 2 0 1 |pllunit_66:257|LPM_COUNTER:4|carrybit3 - 2 B 24 CARRY 0 0 0 1 |pllunit_66:257|LPM_COUNTER:9|carrybit1 - 3 B 24 CARRY 0 2 0 1 |pllunit_66:257|LPM_COUNTER:9|carrybit2 - 4 B 24 CARRY 0 2 0 1 |pllunit_66:257|LPM_COUNTER:9|carrybit3 - 5 B 24 CARRY 0 2 0 1 |pllunit_66:257|LPM_COUNTER:9|carrybit4 Code: s = Synthesized pin or logic cell + = Synchronous flipflop / = Slow slew-rate output ! = NOT gate push-back r = Fitter-inserted logic cell ^ = Increased input delay $ = Driven by fast output logic cell p = Packed register Device-Specific Information:c:\max2work\kumagai\univ_if\uifbase\uif_ramrw_16m.rpt uif_ramrw_16m ** FASTTRACK INTERCONNECT UTILIZATION ** Row FastTrack Interconnect: Global Left Half- Right Half- FastTrack FastTrack FastTrack Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins A: 15/124( 12%) 9/ 62( 14%) 1/ 62( 1%) 4/20( 20%) 0/20( 0%) 7/20( 35%) B: 9/124( 7%) 2/ 62( 3%) 3/ 62( 4%) 0/20( 0%) 2/20( 10%) 5/20( 25%) C: 5/124( 4%) 8/ 62( 12%) 0/ 62( 0%) 0/20( 0%) 0/20( 0%) 9/20( 45%) D: 3/124( 2%) 6/ 62( 9%) 1/ 62( 1%) 6/20( 30%) 6/20( 30%) 1/20( 5%) E: 0/124( 0%) 0/ 62( 0%) 0/ 62( 0%) 1/20( 5%) 5/20( 25%) 7/20( 35%) F: 0/124( 0%) 0/ 62( 0%) 0/ 62( 0%) 5/20( 25%) 2/20( 10%) 2/20( 10%) G: 15/124( 12%) 22/ 62( 35%) 0/ 62( 0%) 0/20( 0%) 0/20( 0%) 9/20( 45%) Column FastTrack Interconnect: FastTrack Column Interconnect Input Pins Output Pins Bidir Pins 01: 8/30( 26%) 0/4( 0%) 0/4( 0%) 2/4( 50%) 02: 1/30( 3%) 0/4( 0%) 0/4( 0%) 2/4( 50%) 03: 4/30( 13%) 0/4( 0%) 0/4( 0%) 2/4( 50%) 04: 4/30( 13%) 0/4( 0%) 2/4( 50%) 0/4( 0%) 05: 0/30( 0%) 0/4( 0%) 0/4( 0%) 1/4( 25%) 06: 0/30( 0%) 2/4( 50%) 0/4( 0%) 1/4( 25%) 07: 1/30( 3%) 1/4( 25%) 0/4( 0%) 2/4( 50%) 08: 0/30( 0%) 2/4( 50%) 0/4( 0%) 1/4( 25%) 09: 2/30( 6%) 1/4( 25%) 0/4( 0%) 1/4( 25%) 10: 2/30( 6%) 1/4( 25%) 0/4( 0%) 2/4( 50%) 11: 1/30( 3%) 2/4( 50%) 1/4( 25%) 0/4( 0%) 12: 2/30( 6%) 1/4( 25%) 1/4( 25%) 0/4( 0%) 13: 0/30( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 14: 1/30( 3%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 15: 2/30( 6%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 16: 2/30( 6%) 0/4( 0%) 0/4( 0%) 1/4( 25%) 17: 4/30( 13%) 0/4( 0%) 0/4( 0%) 2/4( 50%) 18: 3/30( 10%) 2/4( 50%) 0/4( 0%) 1/4( 25%) 19: 1/30( 3%) 1/4( 25%) 0/4( 0%) 1/4( 25%) 20: 2/30( 6%) 0/4( 0%) 0/4( 0%) 2/4( 50%) 21: 1/30( 3%) 2/4( 50%) 0/4( 0%) 1/4( 25%) 22: 1/30( 3%) 2/4( 50%) 0/4( 0%) 0/4( 0%) 23: 0/30( 0%) 1/4( 25%) 1/4( 25%) 0/4( 0%) 24: 0/30( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%) 25: 0/30( 0%) 1/4( 25%) 0/4( 0%) 0/4( 0%) 26: 0/30( 0%) 1/4( 25%) 0/4( 0%) 1/4( 25%) 27: 0/30( 0%) 1/4( 25%) 0/4( 0%) 1/4( 25%) 28: 0/30( 0%) 1/4( 25%) 0/4( 0%) 1/4( 25%) Device-Specific Information:c:\max2work\kumagai\univ_if\uifbase\uif_ramrw_16m.rpt uif_ramrw_16m ** CLOCK SIGNALS ** Type Fan-out Name INPUT 77 BCLK INPUT 7 ExtClock0 Device-Specific Information:c:\max2work\kumagai\univ_if\uifbase\uif_ramrw_16m.rpt uif_ramrw_16m ** SYNCHRONOUS CLEAR SIGNALS ** Type Fan-out Name LCELL 5 |pllunit_66:257|LPM_COUNTER:9|nClr Device-Specific Information:c:\max2work\kumagai\univ_if\uifbase\uif_ramrw_16m.rpt uif_ramrw_16m ** CARRY CHAINS ** Type Member Length Member Name: SUM, (CARRY) COUNTER/FAST FEEDBACK 1 |pllunit_66:257|LPM_COUNTER:9|q0, (|pllunit_66:257|LPM_COUNTER:9|carrybit1) COUNTER/REGULAR FEEDBACK 2 |pllunit_66:257|LPM_COUNTER:9|q1, (|pllunit_66:257|LPM_COUNTER:9|carrybit2) COUNTER/REGULAR FEEDBACK 3 |pllunit_66:257|LPM_COUNTER:9|q2, (|pllunit_66:257|LPM_COUNTER:9|carrybit3) COUNTER/REGULAR FEEDBACK 4 |pllunit_66:257|LPM_COUNTER:9|q3, (|pllunit_66:257|LPM_COUNTER:9|carrybit4) COUNTER/REGULAR FEEDBACK 5 |pllunit_66:257|LPM_COUNTER:9|q4 COUNTER/FAST FEEDBACK 1 |pllunit_66:257|C0, (|pllunit_66:257|LPM_COUNTER:4|carrybit1) ARITHMETIC 2 |pllunit_66:257|C1, (|pllunit_66:257|LPM_COUNTER:4|carrybit2) ARITHMETIC 3 |pllunit_66:257|C2, (|pllunit_66:257|LPM_COUNTER:4|carrybit3) NORMAL 4 |pllunit_66:257|C3 Device-Specific Information:c:\max2work\kumagai\univ_if\uifbase\uif_ramrw_16m.rpt uif_ramrw_16m ** EQUATIONS ** BCLK : INPUT; ExtClock0 : INPUT; ExtClock1 : INPUT; TA0 : INPUT; TA1 : INPUT; TA2 : INPUT; TA3 : INPUT; TA4 : INPUT; TA5 : INPUT; TA6 : INPUT; TA7 : INPUT; TA8 : INPUT; TA9 : INPUT; TA10 : INPUT; TA11 : INPUT; TA12 : INPUT; TA13 : INPUT; TA14 : INPUT; TA15 : INPUT; TA16 : INPUT; /BHE : INPUT; /IOCS0 : INPUT; /IOCS1 : INPUT; /IOCS2 : INPUT; /IOCS3 : INPUT; /IOCS4 : INPUT; /IOCS5 : INPUT; /IOCS6 : INPUT; /IOCS7 : INPUT; /IOR : INPUT; /IORACK : INPUT; /IOW : INPUT; /IRC0 : INPUT; /IRC1 : INPUT; /IRC2 : INPUT; /IRC3 : INPUT; /MEMCS : INPUT; /MRD : INPUT; /MWR : INPUT; /ROMCS : INPUT; /TOUT : INPUT; /TRESET : INPUT; -- Node name is '|ramctrl16:231|~19~1' = 'DR0' -- Equation name is 'DR0', location is LC6_A3, type is buried. DR0 = DFF( _EQ001, GLOBAL( BCLK), VCC, VCC); _EQ001 = DR0 & !_LC1_D1 # DR0 & !_LC3_C1 # IOD4 & _LC1_D1 & _LC3_C1; -- Node name is '|ramctrl16:231|~19~2' = 'DR1' -- Equation name is 'DR1', location is LC1_A1, type is buried. DR1 = DFF( _EQ002, GLOBAL( BCLK), VCC, VCC); _EQ002 = DR1 & !_LC1_D1 # DR1 & !_LC3_C1 # IOD2 & _LC1_D1 & _LC3_C1; -- Node name is '|ramctrl16:231|~19~3' = 'DR2' -- Equation name is 'DR2', location is LC7_A1, type is buried. DR2 = DFF( _EQ003, GLOBAL( BCLK), VCC, VCC); _EQ003 = DR2 & !_LC1_D1 # DR2 & !_LC3_C1 # IOD0 & _LC1_D1 & _LC3_C1; -- Node name is '|ramctrl16:231|~19~4' = 'DR3' -- Equation name is 'DR3', location is LC8_A1, type is buried. DR3 = DFF( _EQ004, GLOBAL( BCLK), VCC, VCC); _EQ004 = DR3 & !_LC1_D1 # DR3 & !_LC3_C1 # IOD1 & _LC1_D1 & _LC3_C1; -- Node name is '|ramctrl16:231|~19~5' = 'DR4' -- Equation name is 'DR4', location is LC9_A1, type is buried. DR4 = DFF( _EQ005, GLOBAL( BCLK), VCC, VCC); _EQ005 = DR4 & !_LC1_D1 # DR4 & !_LC3_C1 # IOD3 & _LC1_D1 & _LC3_C1; -- Node name is '|ramctrl16:231|~19~6' = 'DR5' -- Equation name is 'DR5', location is LC5_A1, type is buried. DR5 = DFF( _EQ006, GLOBAL( BCLK), VCC, VCC); _EQ006 = DR5 & !_LC1_D1 # DR5 & !_LC3_C1 # IOD5 & _LC1_D1 & _LC3_C1; -- Node name is '|ramctrl16:231|~19~7' = 'DR6' -- Equation name is 'DR6', location is LC6_A1, type is buried. DR6 = DFF( _EQ007, GLOBAL( BCLK), VCC, VCC); _EQ007 = DR6 & !_LC1_D1 # DR6 & !_LC3_C1 # IOD7 & _LC1_D1 & _LC3_C1; -- Node name is '|ramctrl16:231|~19~8' = 'DR7' -- Equation name is 'DR7', location is LC4_A1, type is buried. DR7 = DFF( _EQ008, GLOBAL( BCLK), VCC, VCC); _EQ008 = DR7 & !_LC1_D1 # DR7 & !_LC3_C1 # IOE1 & _LC1_D1 & _LC3_C1; -- Node name is '|ramctrl16:231|~32~1' = 'DR8' -- Equation name is 'DR8', location is LC2_A1, type is buried. DR8 = DFF( _EQ009, GLOBAL( BCLK), VCC, VCC); _EQ009 = DR8 & !_LC3_A1 # DR8 & !_LC3_C1 # IOD4 & _LC3_A1 & _LC3_C1; -- Node name is '|ramctrl16:231|~32~2' = 'DR9' -- Equation name is 'DR9', location is LC4_B1, type is buried. DR9 = DFF( _EQ010, GLOBAL( BCLK), VCC, VCC); _EQ010 = DR9 & !_LC3_A1 # DR9 & !_LC3_C1 # IOD2 & _LC3_A1 & _LC3_C1; -- Node name is '|ramctrl16:231|~32~3' = 'DR10' -- Equation name is 'DR10', location is LC3_B1, type is buried. DR10 = DFF( _EQ011, GLOBAL( BCLK), VCC, VCC); _EQ011 = DR10 & !_LC3_A1 # DR10 & !_LC3_C1 # IOD0 & _LC3_A1 & _LC3_C1; -- Node name is '|ramctrl16:231|~32~4' = 'DR11' -- Equation name is 'DR11', location is LC2_B1, type is buried. DR11 = DFF( _EQ012, GLOBAL( BCLK), VCC, VCC); _EQ012 = DR11 & !_LC3_A1 # DR11 & !_LC3_C1 # IOD1 & _LC3_A1 & _LC3_C1; -- Node name is '|ramctrl16:231|~32~5' = 'DR12' -- Equation name is 'DR12', location is LC1_B1, type is buried. DR12 = DFF( _EQ013, GLOBAL( BCLK), VCC, VCC); _EQ013 = DR12 & !_LC3_A1 # DR12 & !_LC3_C1 # IOD3 & _LC3_A1 & _LC3_C1; -- Node name is '|ramctrl16:231|~32~6' = 'DR13' -- Equation name is 'DR13', location is LC4_C1, type is buried. DR13 = DFF( _EQ014, GLOBAL( BCLK), VCC, VCC); _EQ014 = DR13 & !_LC3_A1 # DR13 & !_LC3_C1 # IOD5 & _LC3_A1 & _LC3_C1; -- Node name is '|ramctrl16:231|~32~7' = 'DR14' -- Equation name is 'DR14', location is LC2_C1, type is buried. DR14 = DFF( _EQ015, GLOBAL( BCLK), VCC, VCC); _EQ015 = DR14 & !_LC3_A1 # DR14 & !_LC3_C1 # IOD7 & _LC3_A1 & _LC3_C1; -- Node name is '|ramctrl16:231|~32~8' = 'DR15' -- Equation name is 'DR15', location is LC1_C1, type is buried. DR15 = DFF( _EQ016, GLOBAL( BCLK), VCC, VCC); _EQ016 = DR15 & !_LC3_A1 # DR15 & !_LC3_C1 # IOE1 & _LC3_A1 & _LC3_C1; -- Node name is 'ExtIO0' -- Equation name is 'ExtIO0', type is output ExtIO0 = _LC1_D28; -- Node name is 'ExtIO1' -- Equation name is 'ExtIO1', type is output ExtIO1 = GND; -- Node name is 'IOA_DIR' -- Equation name is 'IOA_DIR', type is output IOA_DIR = GND; -- Node name is 'IOA_EN' -- Equation name is 'IOA_EN', type is output IOA_EN = GND; -- Node name is 'IOA0' -- Equation name is 'IOA0', type is bidir IOA0 = TRI(GND, GND); -- Node name is 'IOA1' -- Equation name is 'IOA1', type is bidir IOA1 = TRI(GND, GND); -- Node name is 'IOA2' -- Equation name is 'IOA2', type is bidir IOA2 = TRI(GND, GND); -- Node name is 'IOA3' -- Equation name is 'IOA3', type is bidir IOA3 = TRI(GND, GND); -- Node name is 'IOA4' -- Equation name is 'IOA4', type is bidir IOA4 = TRI(GND, GND); -- Node name is 'IOA5' -- Equation name is 'IOA5', type is bidir IOA5 = TRI(GND, GND); -- Node name is 'IOA6' -- Equation name is 'IOA6', type is bidir IOA6 = TRI(GND, GND); -- Node name is 'IOA7' -- Equation name is 'IOA7', type is bidir IOA7 = TRI(GND, GND); -- Node name is 'IOB_DIR' -- Equation name is 'IOB_DIR', type is output IOB_DIR = GND; -- Node name is 'IOB_EN' -- Equation name is 'IOB_EN', type is output IOB_EN = GND; -- Node name is 'IOB0' -- Equation name is 'IOB0', type is bidir IOB0 = TRI(GND, GND); -- Node name is 'IOB1' -- Equation name is 'IOB1', type is bidir IOB1 = TRI(GND, GND); -- Node name is 'IOB2' -- Equation name is 'IOB2', type is bidir IOB2 = TRI(GND, GND); -- Node name is 'IOB3' -- Equation name is 'IOB3', type is bidir IOB3 = TRI(GND, GND); -- Node name is 'IOB4' -- Equation name is 'IOB4', type is bidir IOB4 = TRI(GND, GND); -- Node name is 'IOB5' -- Equation name is 'IOB5', type is bidir IOB5 = TRI(GND, GND); -- Node name is 'IOB6' -- Equation name is 'IOB6', type is bidir IOB6 = TRI(GND, GND); -- Node name is 'IOB7' -- Equation name is 'IOB7', type is bidir IOB7 = TRI(GND, GND); -- Node name is 'IOC_DIR' -- Equation name is 'IOC_DIR', type is output IOC_DIR = GND; -- Node name is 'IOC_EN' -- Equation name is 'IOC_EN', type is output IOC_EN = GND; -- Node name is 'IOC0' -- Equation name is 'IOC0', type is bidir IOC0 = TRI(GND, GND); -- Node name is 'IOC1' -- Equation name is 'IOC1', type is bidir IOC1 = TRI(GND, GND); -- Node name is 'IOC2' -- Equation name is 'IOC2', type is bidir IOC2 = TRI(GND, GND); -- Node name is 'IOC3' -- Equation name is 'IOC3', type is bidir IOC3 = TRI(GND, GND); -- Node name is 'IOC4' -- Equation name is 'IOC4', type is bidir IOC4 = TRI(GND, GND); -- Node name is 'IOC5' -- Equation name is 'IOC5', type is bidir IOC5 = TRI(GND, GND); -- Node name is 'IOC6' -- Equation name is 'IOC6', type is bidir IOC6 = TRI(GND, GND); -- Node name is 'IOC7' -- Equation name is 'IOC7', type is bidir IOC7 = TRI(GND, GND); -- Node name is 'IOD_DIR' -- Equation name is 'IOD_DIR', type is output IOD_DIR = GND; -- Node name is 'IOD_EN' -- Equation name is 'IOD_EN', type is output IOD_EN = VCC; -- Node name is 'IOD0' -- Equation name is 'IOD0', type is bidir IOD0 = TRI(_LC6_G21, _LC6_G4); -- Node name is 'IOD1' -- Equation name is 'IOD1', type is bidir IOD1 = TRI(_LC1_G20, _LC6_G4); -- Node name is 'IOD2' -- Equation name is 'IOD2', type is bidir IOD2 = TRI(_LC6_G20, _LC6_G4); -- Node name is 'IOD3' -- Equation name is 'IOD3', type is bidir IOD3 = TRI(_LC6_G19, _LC6_G4); -- Node name is 'IOD4' -- Equation name is 'IOD4', type is bidir IOD4 = TRI(_LC1_G18, _LC6_G4); -- Node name is 'IOD5' -- Equation name is 'IOD5', type is bidir IOD5 = TRI(_LC6_G18, _LC6_G4); -- Node name is 'IOD6' -- Equation name is 'IOD6', type is bidir IOD6 = TRI(_LC6_G17, VCC); -- Node name is 'IOD7' -- Equation name is 'IOD7', type is bidir IOD7 = TRI(_LC6_G16, _LC6_G4); -- Node name is 'IOE_DIR' -- Equation name is 'IOE_DIR', type is output IOE_DIR = GND; -- Node name is 'IOE_EN' -- Equation name is 'IOE_EN', type is output IOE_EN = VCC; -- Node name is 'IOE0' -- Equation name is 'IOE0', type is bidir IOE0 = TRI(_LC6_G11, VCC); -- Node name is 'IOE1' -- Equation name is 'IOE1', type is bidir IOE1 = TRI(_LC6_G10, _LC6_G4); -- Node name is 'IOE2' -- Equation name is 'IOE2', type is bidir IOE2 = TRI(_LC7_G9, VCC); -- Node name is 'IOE3' -- Equation name is 'IOE3', type is bidir IOE3 = TRI(_LC6_G9, VCC); -- Node name is 'IOE4' -- Equation name is 'IOE4', type is bidir IOE4 = TRI(_LC6_G8, VCC); -- Node name is 'IOE5' -- Equation name is 'IOE5', type is bidir IOE5 = TRI(_LC6_G7, VCC); -- Node name is 'IOE6' -- Equation name is 'IOE6', type is bidir IOE6 = TRI(_LC1_G5, VCC); -- Node name is 'IOE7' -- Equation name is 'IOE7', type is bidir IOE7 = TRI(_LC6_G6, VCC); -- Node name is 'IOF_DIR' -- Equation name is 'IOF_DIR', type is output IOF_DIR = !_LC6_G4; -- Node name is 'IOF_EN' -- Equation name is 'IOF_EN', type is output IOF_EN = VCC; -- Node name is 'IOF0' -- Equation name is 'IOF0', type is bidir IOF0 = TRI(_LC1_G3, VCC); -- Node name is 'IOF1' -- Equation name is 'IOF1', type is bidir IOF1 = TRI(_LC1_G2, VCC); -- Node name is 'IOF2' -- Equation name is 'IOF2', type is bidir IOF2 = TRI(_LC1_G1, VCC); -- Node name is 'IOF3' -- Equation name is 'IOF3', type is bidir IOF3 = TRI(_LC5_G1, VCC); -- Node name is 'IOF4' -- Equation name is 'IOF4', type is bidir IOF4 = TRI(_LC4_G1, VCC); -- Node name is 'IOF5' -- Equation name is 'IOF5', type is bidir IOF5 = TRI(_LC3_G1, VCC); -- Node name is 'IOF6' -- Equation name is 'IOF6', type is bidir IOF6 = TRI(_LC2_G1, VCC); -- Node name is 'IOF7' -- Equation name is 'IOF7', type is bidir IOF7 = TRI(_LC6_G1, VCC); -- Node name is 'IORDY' -- Equation name is 'IORDY', type is output IORDY = VCC; -- Node name is 'IRQ0' -- Equation name is 'IRQ0', type is output IRQ0 = GND; -- Node name is 'IRQ1' -- Equation name is 'IRQ1', type is output IRQ1 = GND; -- Node name is 'IRQ2' -- Equation name is 'IRQ2', type is output IRQ2 = GND; -- Node name is 'IRQ3' -- Equation name is 'IRQ3', type is output IRQ3 = GND; -- Node name is '~250~1' = 'MA0' -- Equation name is '~250~1', location is LC6_G5, type is buried. MA0 = DFF( _EQ017, GLOBAL( BCLK), VCC, VCC); _EQ017 = /IOW & MA0 # MA0 & !TA1 # !/IOW & TA1 & TD0; -- Node name is '~250~2' = 'MA1' -- Equation name is '~250~2', location is LC1_D4, type is buried. MA1 = DFF( _EQ018, GLOBAL( BCLK), VCC, VCC); _EQ018 = /IOW & MA1 # MA1 & !TA1 # !/IOW & TA1 & TD1; -- Node name is '~250~3' = 'MA2' -- Equation name is '~250~3', location is LC7_G13, type is buried. MA2 = DFF( _EQ019, GLOBAL( BCLK), VCC, VCC); _EQ019 = /IOW & MA2 # MA2 & !TA1 # !/IOW & TA1 & TD2; -- Node name is '~250~4' = 'MA3' -- Equation name is '~250~4', location is LC10_G1, type is buried. MA3 = DFF( _EQ020, GLOBAL( BCLK), VCC, VCC); _EQ020 = /IOW & MA3 # MA3 & !TA1 # !/IOW & TA1 & TD3; -- Node name is '~250~5' = 'MA4' -- Equation name is '~250~5', location is LC8_G1, type is buried. MA4 = DFF( _EQ021, GLOBAL( BCLK), VCC, VCC); _EQ021 = /IOW & MA4 # MA4 & !TA1 # !/IOW & TA1 & TD4; -- Node name is '~250~6' = 'MA5' -- Equation name is '~250~6', location is LC7_G1, type is buried. MA5 = DFF( _EQ022, GLOBAL( BCLK), VCC, VCC); _EQ022 = /IOW & MA5 # MA5 & !TA1 # !/IOW & TA1 & TD5; -- Node name is '~250~7' = 'MA6' -- Equation name is '~250~7', location is LC2_G11, type is buried. MA6 = DFF( _EQ023, GLOBAL( BCLK), VCC, VCC); _EQ023 = /IOW & MA6 # MA6 & !TA1 # !/IOW & TA1 & TD6; -- Node name is '~250~8' = 'MA7' -- Equation name is '~250~8', location is LC6_G2, type is buried. MA7 = DFF( _EQ024, GLOBAL( BCLK), VCC, VCC); _EQ024 = /IOW & MA7 # MA7 & !TA1 # !/IOW & TA1 & TD7; -- Node name is '~250~9' = 'MA8' -- Equation name is '~250~9', location is LC1_G6, type is buried. MA8 = DFF( _EQ025, GLOBAL( BCLK), VCC, VCC); _EQ025 = /IOW & MA8 # MA8 & !TA1 # !/IOW & TA1 & TD8; -- Node name is '~250~10' = 'MA9' -- Equation name is '~250~10', location is LC6_D4, type is buried. MA9 = DFF( _EQ026, GLOBAL( BCLK), VCC, VCC); _EQ026 = /IOW & MA9 # MA9 & !TA1 # !/IOW & TA1 & TD9; -- Node name is '~250~11' = 'MA10' -- Equation name is '~250~11', location is LC1_G8, type is buried. MA10 = DFF( _EQ027, GLOBAL( BCLK), VCC, VCC); _EQ027 = /IOW & MA10 # MA10 & !TA1 # !/IOW & TA1 & TD10; -- Node name is '~250~12' = 'MA11' -- Equation name is '~250~12', location is LC1_G9, type is buried. MA11 = DFF( _EQ028, GLOBAL( BCLK), VCC, VCC); _EQ028 = /IOW & MA11 # MA11 & !TA1 # !/IOW & TA1 & TD11; -- Node name is '~250~13' = 'MA12' -- Equation name is '~250~13', location is LC7_G11, type is buried. MA12 = DFF( _EQ029, GLOBAL( BCLK), VCC, VCC); _EQ029 = /IOW & MA12 # MA12 & !TA1 # !/IOW & TA1 & TD12; -- Node name is '~250~14' = 'MA13' -- Equation name is '~250~14', location is LC2_D4, type is buried. MA13 = DFF( _EQ030, GLOBAL( BCLK), VCC, VCC); _EQ030 = /IOW & MA13 # MA13 & !TA1 # !/IOW & TA1 & TD13; -- Node name is '~250~15' = 'MA14' -- Equation name is '~250~15', location is LC9_G1, type is buried. MA14 = DFF( _EQ031, GLOBAL( BCLK), VCC, VCC); _EQ031 = /IOW & MA14 # MA14 & !TA1 # !/IOW & TA1 & TD14; -- Node name is 'TCLK' -- Equation name is 'TCLK', type is bidir TCLK = TRI(GND, GND); -- Node name is 'TD0' -- Equation name is 'TD0', type is bidir TD0 = TRI(DR0, !_LC2_A15); -- Node name is 'TD1' -- Equation name is 'TD1', type is bidir TD1 = TRI(DR1, !_LC2_A15); -- Node name is 'TD2' -- Equation name is 'TD2', type is bidir TD2 = TRI(DR2, !_LC2_A15); -- Node name is 'TD3' -- Equation name is 'TD3', type is bidir TD3 = TRI(DR3, !_LC2_A15); -- Node name is 'TD4' -- Equation name is 'TD4', type is bidir TD4 = TRI(DR4, !_LC2_A15); -- Node name is 'TD5' -- Equation name is 'TD5', type is bidir TD5 = TRI(DR5, !_LC2_A15); -- Node name is 'TD6' -- Equation name is 'TD6', type is bidir TD6 = TRI(DR6, !_LC2_A15); -- Node name is 'TD7' -- Equation name is 'TD7', type is bidir TD7 = TRI(DR7, !_LC2_A15); -- Node name is 'TD8' -- Equation name is 'TD8', type is bidir TD8 = TRI(DR8, !_LC2_A15); -- Node name is 'TD9' -- Equation name is 'TD9', type is bidir TD9 = TRI(DR9, !_LC2_A15); -- Node name is 'TD10' -- Equation name is 'TD10', type is bidir TD10 = TRI(DR10, !_LC2_A15); -- Node name is 'TD11' -- Equation name is 'TD11', type is bidir TD11 = TRI(DR11, !_LC2_A15); -- Node name is 'TD12' -- Equation name is 'TD12', type is bidir TD12 = TRI(DR12, !_LC2_A15); -- Node name is 'TD13' -- Equation name is 'TD13', type is bidir TD13 = TRI(DR13, !_LC2_A15); -- Node name is 'TD14' -- Equation name is 'TD14', type is bidir TD14 = TRI(DR14, !_LC2_A15); -- Node name is 'TD15' -- Equation name is 'TD15', type is bidir TD15 = TRI(DR15, !_LC2_A15); -- Node name is '|pllunit_66:257|LPM_COUNTER:4|dffs0' = '|pllunit_66:257|C0' from file "lpm_counter.tdf" line 234, column 10 -- Equation name is '_LC2_D28', type is buried -- |pllunit_66:257|C0 is in Counter Mode _LC2_D28 = DFF(!_LC2_D28, GLOBAL( BCLK), VCC, VCC); -- Node name is '|pllunit_66:257|LPM_COUNTER:4|dffs1' = '|pllunit_66:257|C1' from file "lpm_counter.tdf" line 234, column 10 -- Equation name is '_LC3_D28', type is buried _LC3_D28 = DFF( _EQ032, GLOBAL( BCLK), VCC, VCC); _EQ032 = !_LC2_D28_CARRY & _LC3_D28 # _LC2_D28_CARRY & !_LC3_D28; -- Node name is '|pllunit_66:257|LPM_COUNTER:4|dffs2' = '|pllunit_66:257|C2' from file "lpm_counter.tdf" line 234, column 10 -- Equation name is '_LC4_D28', type is buried _LC4_D28 = DFF( _EQ033, GLOBAL( BCLK), VCC, VCC); _EQ033 = !_LC3_D28_CARRY & _LC4_D28 # _LC3_D28_CARRY & !_LC4_D28; -- Node name is '|pllunit_66:257|LPM_COUNTER:4|dffs3' = '|pllunit_66:257|C3' from file "lpm_counter.tdf" line 234, column 10 -- Equation name is '_LC5_D28', type is buried _LC5_D28 = DFF( _EQ034, GLOBAL( BCLK), VCC, VCC); _EQ034 = !_LC4_D28_CARRY & _LC5_D28 # _LC4_D28_CARRY & !_LC5_D28; -- Node name is '|pllunit_66:257|:6' = '|pllunit_66:257.DiffOut' -- Equation name is '_LC1_D28', type is buried _LC1_D28 = LCELL( _EQ035); _EQ035 = _LC1_B22 & !_LC5_D28 # !_LC1_B22 & _LC5_D28; -- Node name is '|pllunit_66:257|LPM_COUNTER:4|carrybit1' from file "lpm_counter.tdf" line 246, column 14 -- Equation name is '_LC2_D28_CARRY', type is buried -- |pllunit_66:257|LPM_COUNTER:4|carrybit1 is in Counter Mode _LC2_D28_CARRY = CARRY( _LC2_D28); -- Node name is '|pllunit_66:257|LPM_COUNTER:4|carrybit2' from file "lpm_counter.tdf" line 246, column 14 -- Equation name is '_LC3_D28_CARRY', type is buried _LC3_D28_CARRY = CARRY( _EQ036); _EQ036 = _LC2_D28_CARRY & _LC3_D28; -- Node name is '|pllunit_66:257|LPM_COUNTER:4|carrybit3' from file "lpm_counter.tdf" line 246, column 14 -- Equation name is '_LC4_D28_CARRY', type is buried _LC4_D28_CARRY = CARRY( _EQ037); _EQ037 = _LC3_D28_CARRY & _LC4_D28; -- Node name is '|pllunit_66:257|LPM_COUNTER:9|carrybit1' from file "lpm_counter.tdf" line 246, column 14 -- Equation name is '_LC2_B24_CARRY', type is buried -- |pllunit_66:257|LPM_COUNTER:9|carrybit1 is in Counter Mode _LC2_B24_CARRY = CARRY( _LC2_B24); -- Node name is '|pllunit_66:257|LPM_COUNTER:9|carrybit2' from file "lpm_counter.tdf" line 246, column 14 -- Equation name is '_LC3_B24_CARRY', type is buried _LC3_B24_CARRY = CARRY( _EQ038); _EQ038 = _LC2_B24_CARRY & _LC3_B24; -- Node name is '|pllunit_66:257|LPM_COUNTER:9|carrybit3' from file "lpm_counter.tdf" line 246, column 14 -- Equation name is '_LC4_B24_CARRY', type is buried _LC4_B24_CARRY = CARRY( _EQ039); _EQ039 = _LC3_B24_CARRY & _LC4_B24; -- Node name is '|pllunit_66:257|LPM_COUNTER:9|carrybit4' from file "lpm_counter.tdf" line 246, column 14 -- Equation name is '_LC5_B24_CARRY', type is buried _LC5_B24_CARRY = CARRY( _EQ040); _EQ040 = _LC4_B24_CARRY & _LC5_B24; -- Node name is '|pllunit_66:257|LPM_COUNTER:9|lpm_compare:75|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|cmpchain:cmp_end|~40~1' from file "cmpchain.tdf" line 475, column 33 -- Equation name is '_LC8_B24', type is buried -- synthesized logic cell !_LC8_B24 = _LC8_B24~NOT; _LC8_B24~NOT = LCELL( _EQ041); _EQ041 = !_LC4_B24 # !_LC2_B24 # _LC6_B24 # !_LC3_B24; -- Node name is '|pllunit_66:257|LPM_COUNTER:9|lpm_compare:75|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|cmpchain:cmp_end|:40' from file "cmpchain.tdf" line 475, column 33 -- Equation name is '_LC7_B22', type is buried !_LC7_B22 = _LC7_B22~NOT; _LC7_B22~NOT = LCELL( _EQ042); _EQ042 = !_LC5_B24 # !_LC8_B24; -- Node name is '|pllunit_66:257|LPM_COUNTER:9|nClr' from file "lpm_counter.tdf" line 260, column 8 -- Equation name is '_LC7_B24', type is buried _LC7_B24 = LCELL( _EQ043); _EQ043 = !_LC5_B24 # !_LC8_B24; -- Node name is '|pllunit_66:257|LPM_COUNTER:9|dffs0' = '|pllunit_66:257|LPM_COUNTER:9|q0' from file "lpm_counter.tdf" line 234, column 10 -- Equation name is '_LC2_B24', type is buried -- |pllunit_66:257|LPM_COUNTER:9|q0 is in Counter Mode -- synchronous clear = _LC7_B24 _LC2_B24 = DFF(!_LC2_B24 & _LC7_B24, GLOBAL( ExtClock0), VCC, VCC); -- Node name is '|pllunit_66:257|LPM_COUNTER:9|dffs1' = '|pllunit_66:257|LPM_COUNTER:9|q1' from file "lpm_counter.tdf" line 234, column 10 -- Equation name is '_LC3_B24', type is buried -- synchronous clear = _LC7_B24 _LC3_B24 = DFF( _EQ044 & _LC7_B24, GLOBAL( ExtClock0), VCC, VCC); _EQ044 = !_LC2_B24_CARRY & _LC3_B24 # _LC2_B24_CARRY & !_LC3_B24; -- Node name is '|pllunit_66:257|LPM_COUNTER:9|dffs2' = '|pllunit_66:257|LPM_COUNTER:9|q2' from file "lpm_counter.tdf" line 234, column 10 -- Equation name is '_LC4_B24', type is buried -- synchronous clear = _LC7_B24 _LC4_B24 = DFF( _EQ045 & _LC7_B24, GLOBAL( ExtClock0), VCC, VCC); _EQ045 = !_LC3_B24_CARRY & _LC4_B24 # _LC3_B24_CARRY & !_LC4_B24; -- Node name is '|pllunit_66:257|LPM_COUNTER:9|dffs3' = '|pllunit_66:257|LPM_COUNTER:9|q3' from file "lpm_counter.tdf" line 234, column 10 -- Equation name is '_LC5_B24', type is buried -- synchronous clear = _LC7_B24 _LC5_B24 = DFF( _EQ046 & _LC7_B24, GLOBAL( ExtClock0), VCC, VCC); _EQ046 = !_LC4_B24_CARRY & _LC5_B24 # _LC4_B24_CARRY & !_LC5_B24; -- Node name is '|pllunit_66:257|LPM_COUNTER:9|dffs4' = '|pllunit_66:257|LPM_COUNTER:9|q4' from file "lpm_counter.tdf" line 234, column 10 -- Equation name is '_LC6_B24', type is buried -- synchronous clear = _LC7_B24 _LC6_B24 = DFF( _EQ047 & _LC7_B24, GLOBAL( ExtClock0), VCC, VCC); _EQ047 = !_LC5_B24_CARRY & _LC6_B24 # _LC5_B24_CARRY & !_LC6_B24; -- Node name is '|pllunit_66:257|LPM_COUNTER:5|dffs0' = '|pllunit_66:257|V0' from file "lpm_counter.tdf" line 234, column 10 -- Equation name is '_LC6_B22', type is buried _LC6_B22 = DFF( _EQ048, GLOBAL( ExtClock0), VCC, VCC); _EQ048 = _LC6_B22 & !_LC7_B22 # !_LC6_B22 & _LC7_B22; -- Node name is '|pllunit_66:257|LPM_COUNTER:5|dffs1' = '|pllunit_66:257|V1' from file "lpm_counter.tdf" line 234, column 10 -- Equation name is '_LC1_B22', type is buried _LC1_B22 = DFF( _EQ049, GLOBAL( ExtClock0), VCC, VCC); _EQ049 = _LC1_B22 & !_LC5_B24 # _LC1_B22 & !_LC8_B24 # _LC1_B22 & !_LC6_B22 # !_LC1_B22 & _LC5_B24 & _LC6_B22 & _LC8_B24; -- Node name is '|ramctrl16:231|:24' = '|ramctrl16:231.DWE' -- Equation name is '_LC6_G4', type is buried _LC6_G4 = DFF( _EQ050, GLOBAL( BCLK), VCC, VCC); _EQ050 = _LC1_D1 & _LC1_G4 # _LC1_G4 & _LC3_A1; -- Node name is '|ramctrl16:231|~18~1' = '|ramctrl16:231|D8' -- Equation name is '_LC2_G10', type is buried _LC2_G10 = DFF( _EQ051, GLOBAL( BCLK), VCC, VCC); _EQ051 = _LC5_D1 & TD8 # _LC2_G10 & !_LC5_D1; -- Node name is '|ramctrl16:231|~18~2' = '|ramctrl16:231|D9' -- Equation name is '_LC7_D4', type is buried _LC7_D4 = DFF( _EQ052, GLOBAL( BCLK), VCC, VCC); _EQ052 = _LC5_D1 & TD9 # !_LC5_D1 & _LC7_D4; -- Node name is '|ramctrl16:231|~18~3' = '|ramctrl16:231|D10' -- Equation name is '_LC9_G9', type is buried _LC9_G9 = DFF( _EQ053, GLOBAL( BCLK), VCC, VCC); _EQ053 = _LC5_D1 & TD10 # !_LC5_D1 & _LC9_G9; -- Node name is '|ramctrl16:231|~18~4' = '|ramctrl16:231|D11' -- Equation name is '_LC2_G9', type is buried _LC2_G9 = DFF( _EQ054, GLOBAL( BCLK), VCC, VCC); _EQ054 = _LC5_D1 & TD11 # _LC2_G9 & !_LC5_D1; -- Node name is '|ramctrl16:231|~18~5' = '|ramctrl16:231|D12' -- Equation name is '_LC8_G9', type is buried _LC8_G9 = DFF( _EQ055, GLOBAL( BCLK), VCC, VCC); _EQ055 = _LC5_D1 & TD12 # !_LC5_D1 & _LC8_G9; -- Node name is '|ramctrl16:231|~18~6' = '|ramctrl16:231|D13' -- Equation name is '_LC5_C1', type is buried _LC5_C1 = DFF( _EQ056, GLOBAL( BCLK), VCC, VCC); _EQ056 = _LC5_D1 & TD13 # _LC5_C1 & !_LC5_D1; -- Node name is '|ramctrl16:231|~18~7' = '|ramctrl16:231|D14' -- Equation name is '_LC6_C1', type is buried _LC6_C1 = DFF( _EQ057, GLOBAL( BCLK), VCC, VCC); _EQ057 = _LC5_D1 & TD14 # !_LC5_D1 & _LC6_C1; -- Node name is '|ramctrl16:231|~18~8' = '|ramctrl16:231|D15' -- Equation name is '_LC7_C1', type is buried _LC7_C1 = DFF( _EQ058, GLOBAL( BCLK), VCC, VCC); _EQ058 = _LC5_D1 & TD15 # !_LC5_D1 & _LC7_C1; -- Node name is '|ramctrl16:231|:43' = '|ramctrl16:231.MA0' -- Equation name is '_LC7_G9', type is buried _LC7_G9 = DFF( _EQ059, GLOBAL( BCLK), VCC, VCC); _EQ059 = _LC3_A1 # _LC3_A3 # _LC2_A3; -- Node name is '|ramctrl16:231|~11~1' = '|ramctrl16:231.MA1' -- Equation name is '_LC1_G5', type is buried _LC1_G5 = DFF( _EQ060, GLOBAL( BCLK), VCC, VCC); _EQ060 = _LC5_D1 & MA0 # _LC1_G5 & !_LC5_D1; -- Node name is '|ramctrl16:231|~11~2' = '|ramctrl16:231.MA2' -- Equation name is '_LC1_G3', type is buried _LC1_G3 = DFF( _EQ061, GLOBAL( BCLK), VCC, VCC); _EQ061 = _LC5_D1 & MA1 # _LC1_G3 & !_LC5_D1; -- Node name is '|ramctrl16:231|~11~3' = '|ramctrl16:231.MA3' -- Equation name is '_LC1_G1', type is buried _LC1_G1 = DFF( _EQ062, GLOBAL( BCLK), VCC, VCC); _EQ062 = _LC5_D1 & MA2 # _LC1_G1 & !_LC5_D1; -- Node name is '|ramctrl16:231|~11~4' = '|ramctrl16:231.MA4' -- Equation name is '_LC4_G1', type is buried _LC4_G1 = DFF( _EQ063, GLOBAL( BCLK), VCC, VCC); _EQ063 = _LC5_D1 & MA3 # _LC4_G1 & !_LC5_D1; -- Node name is '|ramctrl16:231|~11~5' = '|ramctrl16:231.MA5' -- Equation name is '_LC2_G1', type is buried _LC2_G1 = DFF( _EQ064, GLOBAL( BCLK), VCC, VCC); _EQ064 = _LC5_D1 & MA4 # _LC2_G1 & !_LC5_D1; -- Node name is '|ramctrl16:231|~11~6' = '|ramctrl16:231.MA6' -- Equation name is '_LC3_G1', type is buried _LC3_G1 = DFF( _EQ065, GLOBAL( BCLK), VCC, VCC); _EQ065 = _LC5_D1 & MA5 # _LC3_G1 & !_LC5_D1; -- Node name is '|ramctrl16:231|~11~7' = '|ramctrl16:231.MA7' -- Equation name is '_LC5_G1', type is buried _LC5_G1 = DFF( _EQ066, GLOBAL( BCLK), VCC, VCC); _EQ066 = _LC5_D1 & MA6 # !_LC5_D1 & _LC5_G1; -- Node name is '|ramctrl16:231|~11~8' = '|ramctrl16:231.MA8' -- Equation name is '_LC1_G2', type is buried _LC1_G2 = DFF( _EQ067, GLOBAL( BCLK), VCC, VCC); _EQ067 = _LC5_D1 & MA7 # _LC1_G2 & !_LC5_D1; -- Node name is '|ramctrl16:231|~11~9' = '|ramctrl16:231.MA9' -- Equation name is '_LC6_G6', type is buried _LC6_G6 = DFF( _EQ068, GLOBAL( BCLK), VCC, VCC); _EQ068 = _LC5_D1 & MA8 # !_LC5_D1 & _LC6_G6; -- Node name is '|ramctrl16:231|~11~10' = '|ramctrl16:231.MA10' -- Equation name is '_LC6_G7', type is buried _LC6_G7 = DFF( _EQ069, GLOBAL( BCLK), VCC, VCC); _EQ069 = _LC5_D1 & MA9 # !_LC5_D1 & _LC6_G7; -- Node name is '|ramctrl16:231|~11~11' = '|ramctrl16:231.MA11' -- Equation name is '_LC6_G8', type is buried _LC6_G8 = DFF( _EQ070, GLOBAL( BCLK), VCC, VCC); _EQ070 = _LC5_D1 & MA10 # !_LC5_D1 & _LC6_G8; -- Node name is '|ramctrl16:231|~11~12' = '|ramctrl16:231.MA12' -- Equation name is '_LC6_G9', type is buried _LC6_G9 = DFF( _EQ071, GLOBAL( BCLK), VCC, VCC); _EQ071 = _LC5_D1 & MA11 # !_LC5_D1 & _LC6_G9; -- Node name is '|ramctrl16:231|~11~13' = '|ramctrl16:231.MA13' -- Equation name is '_LC6_G11', type is buried _LC6_G11 = DFF( _EQ072, GLOBAL( BCLK), VCC, VCC); _EQ072 = _LC5_D1 & MA12 # !_LC5_D1 & _LC6_G11; -- Node name is '|ramctrl16:231|~11~14' = '|ramctrl16:231.MA14' -- Equation name is '_LC6_G17', type is buried _LC6_G17 = DFF( _EQ073, GLOBAL( BCLK), VCC, VCC); _EQ073 = _LC5_D1 & MA13 # !_LC5_D1 & _LC6_G17; -- Node name is '|ramctrl16:231|~11~15' = '|ramctrl16:231.MA15' -- Equation name is '_LC6_G1', type is buried _LC6_G1 = DFF( _EQ074, GLOBAL( BCLK), VCC, VCC); _EQ074 = _LC5_D1 & MA14 # !_LC5_D1 & _LC6_G1; -- Node name is '|ramctrl16:231|~36~1~1' = '|ramctrl16~231.MDW0~1' -- Equation name is '_LC1_G10', type is buried -- synthesized logic cell _LC1_G10 = LCELL( _EQ075); _EQ075 = _LC2_A3 & _LC2_G10 # !_LC2_A3 & _LC5_D1 & TD0; -- Node name is '|ramctrl16:231|~36~1' = '|ramctrl16:231.MDW0' -- Equation name is '_LC1_G18', type is buried _LC1_G18 = DFF( _EQ076, GLOBAL( BCLK), VCC, VCC); _EQ076 = _LC1_G18 & !_LC2_A3 & !_LC5_D1 # _LC1_G10; -- Node name is '|ramctrl16:231|~36~2~1' = '|ramctrl16~231.MDW1~1' -- Equation name is '_LC3_D4', type is buried -- synthesized logic cell _LC3_D4 = LCELL( _EQ077); _EQ077 = _LC2_A3 & _LC7_D4 # !_LC2_A3 & _LC5_D1 & TD1; -- Node name is '|ramctrl16:231|~36~2' = '|ramctrl16:231.MDW1' -- Equation name is '_LC6_G20', type is buried _LC6_G20 = DFF( _EQ078, GLOBAL( BCLK), VCC, VCC); _EQ078 = !_LC2_A3 & !_LC5_D1 & _LC6_G20 # _LC3_D4; -- Node name is '|ramctrl16:231|~36~3~1' = '|ramctrl16~231.MDW2~1' -- Equation name is '_LC3_G9', type is buried -- synthesized logic cell _LC3_G9 = LCELL( _EQ079); _EQ079 = _LC2_A3 & _LC9_G9 # !_LC2_A3 & _LC5_D1 & TD2; -- Node name is '|ramctrl16:231|~36~3' = '|ramctrl16:231.MDW2' -- Equation name is '_LC6_G21', type is buried _LC6_G21 = DFF( _EQ080, GLOBAL( BCLK), VCC, VCC); _EQ080 = !_LC2_A3 & !_LC5_D1 & _LC6_G21 # _LC3_G9; -- Node name is '|ramctrl16:231|~36~4~1' = '|ramctrl16~231.MDW3~1' -- Equation name is '_LC4_G9', type is buried -- synthesized logic cell _LC4_G9 = LCELL( _EQ081); _EQ081 = _LC2_A3 & _LC2_G9 # !_LC2_A3 & _LC5_D1 & TD3; -- Node name is '|ramctrl16:231|~36~4' = '|ramctrl16:231.MDW3' -- Equation name is '_LC1_G20', type is buried _LC1_G20 = DFF( _EQ082, GLOBAL( BCLK), VCC, VCC); _EQ082 = _LC1_G20 & !_LC2_A3 & !_LC5_D1 # _LC4_G9; -- Node name is '|ramctrl16:231|~36~5~1' = '|ramctrl16~231.MDW4~1' -- Equation name is '_LC5_G9', type is buried -- synthesized logic cell _LC5_G9 = LCELL( _EQ083); _EQ083 = _LC2_A3 & _LC8_G9 # !_LC2_A3 & _LC5_D1 & TD4; -- Node name is '|ramctrl16:231|~36~5' = '|ramctrl16:231.MDW4' -- Equation name is '_LC6_G19', type is buried _LC6_G19 = DFF( _EQ084, GLOBAL( BCLK), VCC, VCC); _EQ084 = !_LC2_A3 & !_LC5_D1 & _LC6_G19 # _LC5_G9; -- Node name is '|ramctrl16:231|~36~6~1' = '|ramctrl16~231.MDW5~1' -- Equation name is '_LC4_A3', type is buried -- synthesized logic cell _LC4_A3 = LCELL( _EQ085); _EQ085 = _LC2_A3 & _LC5_C1 # !_LC2_A3 & _LC5_D1 & TD5; -- Node name is '|ramctrl16:231|~36~6' = '|ramctrl16:231.MDW5' -- Equation name is '_LC6_G18', type is buried _LC6_G18 = DFF( _EQ086, GLOBAL( BCLK), VCC, VCC); _EQ086 = !_LC2_A3 & !_LC5_D1 & _LC6_G18 # _LC4_A3; -- Node name is '|ramctrl16:231|~36~7~1' = '|ramctrl16~231.MDW6~1' -- Equation name is '_LC7_A3', type is buried -- synthesized logic cell _LC7_A3 = LCELL( _EQ087); _EQ087 = _LC2_A3 & _LC6_C1 # !_LC2_A3 & _LC5_D1 & TD6; -- Node name is '|ramctrl16:231|~36~7' = '|ramctrl16:231.MDW6' -- Equation name is '_LC6_G16', type is buried _LC6_G16 = DFF( _EQ088, GLOBAL( BCLK), VCC, VCC); _EQ088 = !_LC2_A3 & !_LC5_D1 & _LC6_G16 # _LC7_A3; -- Node name is '|ramctrl16:231|~36~8~1' = '|ramctrl16~231.MDW7~1' -- Equation name is '_LC7_G10', type is buried -- synthesized logic cell _LC7_G10 = LCELL( _EQ089); _EQ089 = _LC2_A3 & _LC7_C1 # !_LC2_A3 & _LC5_D1 & TD7; -- Node name is '|ramctrl16:231|~36~8' = '|ramctrl16:231.MDW7' -- Equation name is '_LC6_G10', type is buried _LC6_G10 = DFF( _EQ090, GLOBAL( BCLK), VCC, VCC); _EQ090 = !_LC2_A3 & !_LC5_D1 & _LC6_G10 # _LC7_G10; -- Node name is '|ramctrl16:231|~20~1' = '|ramctrl16:231|Phase0~1' -- Equation name is '_LC4_D1', type is buried -- synthesized logic cell _LC4_D1 = LCELL( _EQ091C); _EQ091C = _EQ091; _EQ091 = !_LC2_D1 & !_LC3_A1 & !_LC6_D1; -- Node name is '|ramctrl16:231|:20' = '|ramctrl16:231|Phase0' -- Equation name is '_LC5_D1', type is buried _LC5_D1 = LCELL( _EQ092C); _EQ092C = _EQ092 & CASCADE( _EQ091C); _EQ092 = !_LC2_A3 & _LC3_D1 # !/IOW & !_LC2_A3 & !TA1; -- Node name is '|ramctrl16:231|:12' = '|ramctrl16:231|Phase1' -- Equation name is '_LC6_D1', type is buried _LC6_D1 = DFF( _LC5_D1, GLOBAL( BCLK), VCC, VCC); -- Node name is '|ramctrl16:231|:21' = '|ramctrl16:231|Phase2' -- Equation name is '_LC1_D1', type is buried _LC1_D1 = DFF( _LC6_D1, GLOBAL( BCLK), VCC, VCC); -- Node name is '|ramctrl16:231|:22' = '|ramctrl16:231|Phase3' -- Equation name is '_LC2_A3', type is buried _LC2_A3 = DFF( _LC1_D1, GLOBAL( BCLK), VCC, VCC); -- Node name is '|ramctrl16:231|:39' = '|ramctrl16:231|Phase4' -- Equation name is '_LC3_A3', type is buried _LC3_A3 = DFF( _LC2_A3, GLOBAL( BCLK), VCC, VCC); -- Node name is '|ramctrl16:231|:40' = '|ramctrl16:231|Phase5' -- Equation name is '_LC3_A1', type is buried _LC3_A1 = DFF( _LC3_A3, GLOBAL( BCLK), VCC, VCC); -- Node name is '|ramctrl16:231|:53' = '|ramctrl16:231|RDEL' -- Equation name is '_LC3_C1', type is buried _LC3_C1 = DFF( _EQ093, GLOBAL( BCLK), VCC, VCC); _EQ093 = _LC3_C1 # _LC5_D1; -- Node name is '|ramctrl16:231|:52' = '|ramctrl16:231|WREL' -- Equation name is '_LC1_G4', type is buried _LC1_G4 = DFF( _EQ094, GLOBAL( BCLK), VCC, VCC); _EQ094 = !/IOW & _LC5_D1 & !TA1 # _LC1_G4 & !_LC5_D1; -- Node name is '|ramctrl16:231|:29' -- Equation name is '_LC2_D1', type is buried _LC2_D1 = DFF( _EQ095, GLOBAL( BCLK), VCC, VCC); _EQ095 = _LC3_D1 # !/IOW & !TA1; -- Node name is '/IOCS2~fit~out' -- Equation name is '/IOCS2~fit~out', location is LC2_A15, type is buried. -- synthesized logic cell _LC2_A15 = LCELL( /IOCS2); -- Node name is '/IORREQ' -- Equation name is '/IORREQ', type is output /IORREQ = VCC; -- Node name is ':253' -- Equation name is '_LC3_D1', type is buried _LC3_D1 = DFF( _EQ096, GLOBAL( BCLK), VCC, VCC); _EQ096 = !/IOW & TA1; Project Information c:\max2work\kumagai\univ_if\uifbase\uif_ramrw_16m.rpt ** COMPILATION SETTINGS & TIMES ** Processing Menu Commands ------------------------ Design Doctor = off Logic Synthesis: Synthesis Type Used = Multi-Level Default Synthesis Style = FAST Logic option settings in 'FAST' style for 'FLEX6000' family CARRY_CHAIN = auto CARRY_CHAIN_LENGTH = 32 CASCADE_CHAIN = auto CASCADE_CHAIN_LENGTH = 2 DECOMPOSE_GATES = on DUPLICATE_LOGIC_EXTRACTION = on MINIMIZATION = full MULTI_LEVEL_FACTORING = on NOT_GATE_PUSH_BACK = on REDUCE_LOGIC = on REFACTORIZATION = off REGISTER_OPTIMIZATION = on RESYNTHESIZE_NETWORK = on SLOW_SLEW_RATE = off SUBFACTOR_EXTRACTION = off IGNORE_SOFT_BUFFERS = on USE_LPM_FOR_AHDL_OPERATORS = off Other logic synthesis settings: Automatic Global Clock = on Automatic Global Clear = on Automatic Global Preset = on Automatic Global Output Enable = on Automatic Fast I/O = on Automatic Register Packing = on Automatic Open-Drain Pins = on Automatic Implement in EAB = off Optimize = 10 Default Timing Specifications: None Cut All Bidir Feedback Timing Paths = on Cut All Clear & Preset Timing Paths = on Ignore Timing Assignments = on Functional SNF Extractor = off Linked SNF Extractor = off Timing SNF Extractor = on Optimize Timing SNF = off Generate AHDL TDO File = off Fitter Settings = NORMAL Smart Recompile = off Total Recompile = off Interfaces Menu Commands ------------------------ EDIF Netlist Writer = off Verilog Netlist Writer = off VHDL Netlist Writer = off Compilation Times ----------------- Compiler Netlist Extractor 00:00:04 Database Builder 00:00:01 Logic Synthesizer 00:00:01 Partitioner 00:00:01 Fitter 00:00:08 Timing SNF Extractor 00:00:00 Assembler 00:00:03 -------------------------- -------- Total Time 00:00:18 Memory Allocated ----------------- Peak memory allocated during compilation = 23,001K